74LVQ74SJ ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-FlopFeaturesThe LVQ74 is a dual D-type flip-flop with Asynchronous
74LVQ74SC-74LVQ74SCX-74LVQ74SJ
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop February 1992 Revised June 2001 74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description Features The LVQ74 is a dual D-type flip-flop with AsynchronousIdeal for low power/low noise 3.3V applications Clear and Set inputs and complementary (Q, Q) outputs.Guaranteed simultaneous switching noise level and Information at the input is transferred to the outputs on the dynamic threshold performance positive edge of the clock pulse. Clock triggering occurs at Guaranteed pin-to-pin skew AC performance a voltage level of the clock pulse and is not directly related Guaranteed incident wave switching into 75Ω to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S (Set) sets Q to HIGH level D LOW input to C (Clear) sets Q to LOW level D Clear and Set are independent of clock Simultaneous LOW on C and S makes both D D Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74LVQ74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVQ74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D , D Data Inputs 1 2 CP , CP Clock Pulse Inputs 1 2 C , C Direct Clear Inputs D1 D2 S , S Direct Set Inputs D1 D2 Q , Q , Q , Q Outputs 1 1 2 2 © 2001 DS011347
