74LVQ573SC ,Low Voltage Octal Latch with 3-STATE Outputsapplicationsmon Latch Enable (LE) and buffered common Output
74LVQ573SC-74LVQ573SCX
Low Voltage Octal Latch with 3-STATE Outputs
74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs February 1992 Revised June 2001 74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs General Description Features The LVQ573 is a high-speed octal latch with buffered com-Ideal for low power/low noise 3.3V applications mon Latch Enable (LE) and buffered common OutputImplements patented EMI reduction circuitry Enable (OE) inputs. The LVQ573 is functionally identical to Available in SOIC JEDEC, SOIC EIAJ, and QSOP the LVQ373 but with inputs and outputs on opposite sides packages of the package. Guaranteed simultaneous switching noise level and dynamic threshold performance Improved latch-up immunity Guaranteed incident wave switching into 75Ω 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74LVQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ573QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Truth Table Inputs Outputs OE LE D O n Pin Descriptions LH H H LH L L Pin Names Description LL X O D –D Data Inputs 0 7 0 HX X Z LE Latch Enable Input H = HIGH Voltage L = LOW Voltage OE 3-STATE Output Enable Input Z = High Impedance X = Immaterial O –O 3-STATE Latch Outputs 0 7 O = Previous O before HIGH-to-LOW transition of Latch Enable 0 0 © 2001 DS011361
