74LVCH162244ADGG ,16-bit buffer/line driver; with 30ohm series termination resistors, 5V input/output tolerant 3-StateFeatures and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply volt ..
74LVCH162244ADGG ,16-bit buffer/line driver; with 30ohm series termination resistors, 5V input/output tolerant 3-State
74LVCH162244ADGG ,16-bit buffer/line driver; with 30ohm series termination resistors, 5V input/output tolerant 3-State
74LVCH162244ADL ,16-bit buffer/line driver; 30 惟 series termination resistors; 5 V tolerant input/output; 3-state
74LVCH162244ADLRG4 ,16-Bit Buffer/Driver With 3-State Outputs 48-SSOP -40 to 125 SCAS545L–OCTOBER 1995–REVISED JUNE 20146 Pin Configuration and FunctionsDL, DGG, OR DGV PACKAGE(TO ..
74LVCH162245ADGG ,16-bit bus transceiver with direction pin; 30ohm series termination resistors; 5V Input/Outputs tolerant 3-StateGeneral descriptionThe 74LVC162245A; 74LVCH162245A are 16-bit transceivers with non-inverting 3-sta ..
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82C55 ,CMOS PROGRAMMABLE PERIPHERAL INTERFACEFEATURESThe TMP82C55A (hereinafter referred to as PPI) is a CMOS high Speedprogrammable input/outpu ..
82C55 ,CMOS PROGRAMMABLE PERIPHERAL INTERFACE
74LVC162244ADGG-74LVCH162244ADGG
16-bit buffer/line driver; 30 惟 series termination resistors; 5 V tolerant input/output; 3-state
1. General descriptionThe 74LVC162244A; 74LVCH162244A are 16-bit non-inverting buffer/line drivers with
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state. The device is designed with 30 series termination resistors
in both HIGH and LOW output stages to reduce line noise.
Inputs can be driven from either 3.3Vor5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3V and5 V applications.
The 74LVCH162244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 Vto 3.6V CMOS low power consumption Multibyte flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground
bounce Direct interface with TTL levels High-impedance when VCC =0V All data inputs have bus hold. (74LVCH162244A only) Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 Cto+85C and 40 Cto+125C
74L VC162244A; 74L VCH162244A
16-bit buffer/line driver; 30 series termination resistors; 5 V
tolerant input/output; 3-state
Rev. 6 — 16 December 2011 Product data sheet
NXP Semiconductors 74L VC162244A; 74L VCH162244A
16-bit buffer/line driver; 30 resistors; 5 V tolerance; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information74LVC162244ADL 40Cto +125 C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVCH162244ADL
74LVC162244ADGG 40 Cto+125C TSSOP48 plastic thin shrink small outline package; leads; body width 6.1 mm
SOT362-1
74LVCH162244ADGG
NXP Semiconductors 74L VC162244A; 74L VCH162244A
16-bit buffer/line driver; 30 resistors; 5 V tolerance; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description1OE 1 output enable input (active LOW)
2OE 48 output enable input (active LOW)
3OE 25 output enable input (active LOW)
4OE 24 output enable input (active LOW)
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC 7, 18, 31, 42 supply voltage
1A[0:3] 47, 46, 44, 43 data input
2A[0:3] 41, 40, 38, 37 data input
3A[0:3] 36, 35, 33, 32 data input
4A[0:3] 30, 29, 27, 26 data input
1Y[0:3] 2, 3, 5, 6 data output
NXP Semiconductors 74L VC162244A; 74L VCH162244A
16-bit buffer/line driver; 30 resistors; 5 V tolerance; 3-state
6. Functional description[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
2Y[0:3] 8, 9, 11, 12 data output
3Y[0:3] 13, 14, 16, 17 data output
4Y[0:3] 19, 20, 22, 23 dataoutput
Table 2. Pin description …continued
Table 3. Function table[1]LLL H Z
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0V - 50 mA output voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V output current VO =0V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125 C; [3] -500 mW
NXP Semiconductors 74L VC162244A; 74L VCH162244A
16-bit buffer/line driver; 30 resistors; 5 V tolerance; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditionsVCC supply voltage 1.65 - 3.6 V
functional 1.2 - 3.6 V input voltage 0 - 5.5 V output voltage output HIGH or LOW 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC- - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3- V= 2 mA; VCC = 1.65 V 1.2 - - 1.05 - V= 4mA; VCC = 2.3V 1.7 - - 1.55 - V= 6mA; VCC = 2.7 V 2.2 - - 2.05 - V= 12 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V - 0.2- 0.3V =2mA; VCC = 1.65 V - - 0.45 - 0.65 V =4mA; VCC = 2.3V - - 0.6 - 0.8 V =6mA; VCC = 2.7 V - - 0.4 - 0.6 V =12mA; VCC = 3.0 V - - 0.55 - 0.8 V input
leakage
current
VCC = 3.6 V; =5.5V orGND 0.1 5- 20 A
NXP Semiconductors 74L VC162244A; 74L VCH162244A
16-bit buffer/line driver; 30 resistors; 5 V tolerance; 3-state[1] All typical values are measured at VCC=3.3 V and Tamb =25C.
[2] The bus hold circuit is switched off when VI >VCC allowing 5.5 V on the input terminal.
[3] Valid for data inputs only. Control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data input holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
IOZ OFF-state
output
current =VIHor VIL; VCC= 3.6 V; =5.5V orGND;
[2] - 0.1 5- 20 A
IOFF power-off
leakage
current
VCC = 0 V; VIorVO = 5.5V - 0.1 10 - 20 A
ICC supply
current
VCC = 3.6 V; =VCCor GND; IO =0A
-0.1 20 - 80 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6 V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC 5.0 -- -pF
IBHL bus hold
LOW current
VCC = 1.65; VI = 0.58 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
IBHH bus hold
HIGH current
VCC = 1.65; VI = 1.07 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold
LOW
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
IBHHO bus hold
HIGH
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continuedAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74L VC162244A; 74L VCH162244A
16-bit buffer/line driver; 30 resistors; 5 V tolerance; 3-state
10. Dynamic characteristics[1] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fiN+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs.
Table 7. Dynamic characteristicsVoltages are referenced to GND (ground=0 V). For test circuit see Figure7.
tpd propagation
delay
nAntonYn; see Figure5 [1]
VCC= 1.2V - 11.0 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.0 15.0 1.5 17.2 ns
VCC = 2.3 V to 2.7 V 1.0 3.2 7.4 1.0 8.2 ns
VCC = 2.7 V 1.0 3.3 6.7 1.0 8.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.7 5.8 1.0 7.5 ns
ten enable time nOEto nYn; see Figure6 [1]
VCC= 1.2V - 15.0 - - - ns
VCC = 1.65 V to 1.95 V 1.7 6.8 15.3 1.7 17.7 ns
VCC = 2.3 V to 2.7 V 1.5 3.8 8.0 1.5 8.9 ns
VCC = 2.7 V 1.5 4.2 7.6 1.5 9.5 ns
VCC = 3.0 V to 3.6 V 1.0 3.1 6.0 1.0 7.5 ns
tdis disable time nOEto nYn; see Figure6 [1]
VCC= 1.2V - 10.0 - - - ns
VCC = 1.65 V to 1.95 V 2.2 3.9 8.2 2.2 9.5 ns
VCC = 2.3 V to 2.7 V 0.5 2.1 4.4 0.5 5.0 ns
VCC = 2.7 V 1.5 3.1 4.7 1.5 6.0 ns
VCC = 3.0 V to 3.6 V 1.5 2.8 4.5 1.5 6.0 ns
CPD power
dissipation
capacitance
per input; VI =GNDto VCC [3]
VCC = 1.65 V to 1.95 V - 4.8 - - - pF
VCC = 2.3 V to 2.7 V - 8.3 - - - pF
VCC = 3.0 V to 3.6 V - 11.4 - - - pF
