74LVC38AD-74LVC38APW Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC38AD-74LVC38APW
Quad 2-input NAND gate; open-drain
1. General description
The 74LVC38A provides four 2-input NAND functions. The outputs are open-drain and
can be connected to other open-drain outputs to implement active-LOW wired-OR or
active-HIGH wired-AND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 5.5V CMOS low power consumption Direct interface with TTL levels Open-drain outputs Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V JESD8-5A (2.3Vto 2.7V JESD8-C/JESD36 (2.7Vto 3.6V ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 Cto+85C and 40 Cto+125C
3. Ordering information
74L VC38A
Quad 2-input NAND gate; open-drain
Rev. 4 — 4 November 2011 Product data sheet
Table 1. Ordering information
74LVC38AD 40 Cto +125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC38ADB 40 Cto +125C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
74LVC38APW 40 Cto +125C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
74LVC38ABQ 40 Cto +125C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
SOT762-1
NXP Semiconductors 74L VC38A
Quad 2-input NAND gate; open-drain
4. Functional diagram
5. Pinning information
5.1 Pinning
NXP Semiconductors 74L VC38A
Quad 2-input NAND gate; open-drain
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; Z = high-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C the value of Ptotderates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C the value of Ptotderates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 2. Pin description
1A, 2A, 3A, 4A 1, 4, 9, 12 data input
1B, 2B, 3B, 4B 2, 5, 10, 13 data input , 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0V)
VCC 14 supply voltage
Table 3. Function selection[1]
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO < 0 50 - mA output voltage active mode [2] 0.5 +6.5 V
high-impedance mode [2] 0.5 +6.5 V output current VO = 0 V to VCC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [3] -500 mW
NXP Semiconductors 74L VC38A
Quad 2-input NAND gate; open-drain
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
VCC supply voltage 1.65 - 5.5 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage active mode 0 - VCC V
high-impedance mode 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall
rate
VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65  VCC- - 0.65  VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7  VCC - - 0.7  VCC -V
VIL LOW-level input
voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35  VCC -0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.30  VCC -0.30  VCCV
VOL LOW-level
output voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 5.5 V - 0.20 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V =32mA; VCC = 4.5 V - - 0.55 - 0.8 V input leakage
current =5.5V orGND;
VCC= 1.65 Vto 5.5 V 0.1 5- 20 A
IOZ OFF-state
output current =VIH; VO = 5.5 V or GND;
VCC= 1.65 V to 5.5 V
-0.1 5- 20 A
IOFF power-off
leakage currentorVO= 5.5 V; VCC =0V - 0.1 10 - 20 A
NXP Semiconductors 74L VC38A
Quad 2-input NAND gate; open-drain
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
ICC supply current VI =VCCor GND; IO =0A;
VCC = 5.5 V
-0.1 10 -40 A
ICC additional
supply current
per input pin; =VCC 0.6 V; IO =0A;
VCC= 2.7Vto 5.5 V 5 500 - 5000 A input
capacitance
VCC= 0 V to 5.5V; =GNDto VCC 4.0 -- -pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure7.
tPZL OFF-state to LOW
propagation delay
nA, nB to nY; see Figure6
VCC = 1.2 V - 5.7 - - - ns
VCC = 1.65 V to 1.95 V 1.0 2.6 6.0 1.0 6.9 ns
VCC = 2.3 V to 2.7 V 0.5 1.8 3.3 0.5 3.8 ns
VCC = 2.7 V 0.5 1.7 2.9 0.5 4.0 ns
VCC = 3.0 V to 3.6 V 0.5 1.8 3.0 0.5 4.0 ns
tPLZ LOW to OFF-state
propagation delay
nA, nB to nY; see Figure6
VCC = 1.2 V - 5.7 - - - ns
VCC = 1.65 V to 1.95 V 1.0 2.7 6.0 1.0 6.9 ns
VCC = 2.3 V to 2.7 V 0.5 1.5 3.3 0.5 3.8 ns
VCC = 2.7 V 1.0 2.6 3.8 1.0 5.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.3 3.6 1.0 4.5 ns
tsk(o) output skew time [2] - - 1.0 - 1.5 ns
NXP Semiconductors 74L VC38A
Quad 2-input NAND gate; open-drain
[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fiN+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs
11. AC waveforms
CPD power dissipation
capacitance
per gate; VI =GNDto VCC [3]
VCC = 1.65 V to 1.95 V - 6.2 - - - pF
VCC = 2.3 V to 2.7 V - 9.7 - - - pF
VCC = 3.0 V to 3.6 V - 12.9 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure7.
Table 8. Measurement points
<2.7 V 0.5  VCC VOL + 0.15 V
2.7 V to 3.6 V 1.5 V VOL + 0.3 V
NXP Semiconductors 74L VC38A
Quad 2-input NAND gate; open-drain
Table 9. Test data
1.2V VCC  2 ns 30pF 1 k open 2  VCC
1.65Vto 1.95V VCC  2 ns 30pF 1 k open 2  VCC
2.3Vto2.7V VCC  2 ns 30pF 500 open 2  VCC
2.7V 2.7V  2.5ns 50pF 500 open 2  VCC
3.0Vto 3.6V 2.7V  2.5ns 50pF 500 open 2  VCC

Partno	Mfg	Dc	Qty	Available	Descript
74LVC38AD	NXP	N/a	2329	avai	74LVC38A; Quad 2-input NAND gate (open drain)
74LVC38APW	NXP/PHILIPS	N/a	3000	avai	Quad 2-input NAND gate; open-drain
74LVC38APW	NXP	N/a	300	avai	Quad 2-input NAND gate; open-drain