74LVC2G86DP-74LVC2G86GD Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC2G86DP-74LVC2G86GD
Dual 2-input EXCLUSIVE-OR gate
1. General description
The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65 V to 5.5V5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95V) JESD8-5 (2.3 V to 2.7V) JESD8B/JESD36 (2.7 V to 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V 24 mA output drive (VCC =3.0V) CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options Specified from 40 C to +85 C and 40 C to +125C
74L VC2G86
Dual 2-input EXCLUSIVE-OR gate
Rev. 11 — 8 April 2013 Product data sheet
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
74LVC2G86DP 40Cto +125C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width3 mm; lead length 0.5 mm
SOT505-2
74LVC2G86DC 40Cto +125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G86GT 40Cto +125C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1  1.95  0.5 mm
SOT833-1
74LVC2G86GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74LVC2G86GD 40Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74LVC2G86GM 40Cto +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6  1.6  0.5 mm
SOT902-2
74LVC2G86GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.2 1.0 0.35 mm
SOT1116
74LVC2G86GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74LVC2G86DP V86
74LVC2G86DC V86
74LVC2G86GT V86
74LVC2G86GF VH
74LVC2G86GD V86
74LVC2G86GM V86
74LVC2G86GN VH
74LVC2G86GS VH
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
5. Functional diagram
6. Pinning information
6.1 Pinning
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level
Table 3. Pin description
1A, 2A 1, 5 7, 3 data input
1B, 2B 2, 6 6, 2 data input
GND 4 4 ground (0V), 2Y 7, 3 1, 5 data output
VCC 8 8 supply voltage
Table 4. Function table[1]
LLL H H
HHL
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 300 mW
Tstg storage temperature 65 +150 C
Table 6. Operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 VCC V
VCC = 0 V; Power-down mode 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V
VCC = 2.7 V to 5.5 V - 10 ns/V
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
10. Static characteristicsTable 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb= 40 Cto+85 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
VOL LOW-level output voltage VI =VIHorVIL =100 A; VCC = 1.65 V to 5.5 V - - 0.1 V =4mA; VCC = 1.65 V - 0.07 0.45 V =8mA; VCC = 2.3 V - 0.12 0.3 V =12mA; VCC = 2.7 V - 0.17 0.4 V =24mA; VCC = 3.0 V - 0.33 0.55 V =32mA; VCC = 4.5 V - 0.39 0.55 V
VOH HIGH-level output voltage VI =VIHorVIL= 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V= 4mA; VCC = 1.65 V 1.2 1.54 - V= 8mA; VCC = 2.3 V 1.9 2.15 - V= 12 mA; VCC = 2.7 V 2.2 2.50 - V= 24 mA; VCC = 3.0 V 2.3 2.62 - V= 32 mA; VCC = 4.5 V 3.8 4.11 - V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - 0.1 5 A
IOFF power-off leakage current VI or VO =5.5 V; VCC =0 V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A
-0.1 10 A
ICC additional supply current per pin; VI =VCC 0.6 V; IO =0A;
VCC = 2.3 V to 5.5 V 5 500 A input capacitance - 2.5 - pF
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
[1] All typical values are measured at VCC=3.3 V and Tamb =25C.
Tamb= 40Cto +125C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
VOL LOW-level output voltage VI =VIHorVIL =100 A; VCC = 1.65 V to 5.5 V - - 0.1 V =4mA; VCC = 1.65 V - - 0.70 V =8mA; VCC = 2.3 V - - 0.45 V =12mA; VCC = 2.7 V - - 0.60 V =24mA; VCC = 3.0 V - - 0.80 V =32mA; VCC = 4.5 V - - 0.80 V
VOH HIGH-level output voltage VI =VIHorVIL= 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V= 4mA; VCC = 1.65 V 0.95 - - V= 8mA; VCC = 2.3 V 1.7 - - V= 12 mA; VCC = 2.7 V 1.9 - - V= 24 mA; VCC = 3.0 V 2.0 - - V= 32 mA; VCC = 4.5 V 3.4 - - V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - - 20 A
IOFF power-off leakage current VI or VO =5.5 V; VCC =0 V - - 20 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A 40 A
ICC additional supply current per pin; VI =VCC 0.6 V; IO =0A;
VCC = 2.3 V to 5.5 V 5000 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
12. Waveforms
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground 0 V); for test circuit see Figure9.
tpd propagation delay nA, nB to nY; see Figure8 [2]
VCC= 1.65Vto 1.95V 1.4 3.8 9.9 1.4 12.4 ns
VCC= 2.3Vto 2.7V 0.8 2.5 5.7 0.8 7.2 ns
VCC= 2.7V 0.8 3.0 5.7 0.8 7.2 ns
VCC= 3.0Vto 3.6V 0.8 2.3 4.7 0.8 5.9 ns
VCC= 4.5Vto 5.5V 0.6 1.9 3.6 0.6 4.5 ns
CPD power dissipation
capacitance
per gate; VI = GND to VCC;
VCC =3.3V
[3]
output enabled - 15.8 - - - pF
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
Table 9. Measurement points
1.65 V to 1.95 V 0.5  VCC 0.5  VCC
2.3 V to 2.7 V 0.5  VCC 0.5  VCC
2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 1.5 V 1.5 V
4.5 V to 5.5 V 0.5  VCC 0.5  VCC
Table 10. Test data
1.65 V to 1.95 V VCC  2.0 ns 30 pF 1 k open
2.3 V to 2.7 V VCC  2.0 ns 30 pF 500  open
2.7 V 2.7 V  2.5 ns 50 pF 500  open
3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open
4.5 V to 5.5 V VCC  2.5 ns 50 pF 500  open
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
13. Package outline
NXP Semiconductors 74LVC2G86
Dual 2-input EXCLUSIVE-OR gate

Partno	Mfg	Dc	Qty	Available	Descript
74LVC2G86DP	NXP	N/a	2034	avai	Dual 2-input EXCLUSIVE-OR gate
74LVC2G86GD	NXP/PHILIPS	N/a	6000	avai	Dual 2-input EXCLUSIVE-OR gate