74LVC2G66DP ,Bilateral switch
74LVC2G66DP ,Bilateral switch 74LVC2G66Bilateral switchRev. 8 — 2 April 2013 Product data sheet1.
74LVC2G66DP ,Bilateral switchFeatures and benefits Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 ..
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74LVC2G66DC-74LVC2G66DP-74LVC2G66GD-74LVC2G66GT
Bilateral switch
1. General descriptionThe 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device.
The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits Wide supply voltage range from 1.65 V to 5.5V Very low ON resistance: 7.5 (typical) at VCC =2.7V 6.5 (typical) at VCC =3.3V6 (typical) at VCC =5V Switch current capability of 32 mA High noise immunity CMOS low power consumption TTL interface compatibility at 3.3 V Latch-up performance meets requirements of JESD78 ClassI ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Enable input accepts voltages up to 5.5 V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
74L VC2G66
Bilateral switch
Rev. 8 — 2 April 2013 Product data sheet
NXP Semiconductors 74LVC2G66
Bilateral switch
3. Ordering information
4. Marking[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information74LVC2G66DP 40Cto +125C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G66DC 40Cto +125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G66GT 40Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 1 1.95 0.5 mm
SOT833-1
74LVC2G66GD 40Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3 2 0.5 mm
SOT996-2
74LVC2G66GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
Table 2. Marking codes74LVC2G66DP V66
74LVC2G66DC V66
74LVC2G66GT V66
74LVC2G66GD V66
74LVC2G66GM V66
NXP Semiconductors 74LVC2G66
Bilateral switch
6. Pinning information
6.1 PinningNXP Semiconductors 74LVC2G66
Bilateral switch
6.2 Pin description
7. Functional description[1] H= HIGH voltage level; L= LOW voltage level.
8. Limiting values[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 3. Pin description 1 7 independent input or output 2 6 independent input or output 3 5 enable input (active HIGH)
GND 4 4 ground (0V) 5 3 independent input or output 6 2 independent input or output 7 1 enable input (active HIGH)
VCC 8 8 supply voltage
Table 4. Function table[1]LOFF-state ON-state
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground= 0 V).
VCC supply voltage 0.5 +6.5 V input voltage [1] 0.5 +6.5 V
IIK input clamping current VI< 0.5 V or VI >VCC +0.5V 50 - mA
ISK switch clamping current VI< 0.5 V or VI >VCC +0.5V - 50 mA
VSW switch voltage enable and disable mode [2] 0.5 VCC +0.5 V
ISW switch current VSW> 0.5 V or
VSW
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 Cto+125C [3] -250 mW
NXP Semiconductors 74LVC2G66
Bilateral switch
9. Recommended operating conditions
[1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no
limit for the voltage drop across the switch.
[2] For overvoltage tolerant switch voltage capability, refer to 74LVCV2G66.
[3] Applies to control signal levels.
10. Static characteristics
Table 6. Operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V
VSW switch voltage [1][2] 0VCC V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC =1.65Vto2.7V [3]- 20 ns/V
VCC= 2.7Vto 5.5V [3]- 10 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC= 1.65Vto 1.95V 0.65 VCC - - 0.65 VCC -V
VCC= 2.3Vto 2.7V 1.7 - - 1.7 - V
VCC= 2.7Vto 3.6V 2.0 - - 2.0 - V
VCC= 4.5Vto 5.5V 0.7 VCC - - 0.7 VCC -V
VIL LOW-level
input voltage
VCC= 1.65Vto 1.95V - - 0.35 VCC - 0.35 VCCV
VCC= 2.3Vto 2.7V - - 0.7 - 0.7 V
VCC= 2.7Vto 3.6V - - 0.8 - 0.8 V
VCC= 4.5Vto 5.5V - - 0.3 VCC -0.3 VCC V input leakage
current
pin nE; VI= 5.5Vor GND;
VCC=0V to 5.5V
[2] - 0.1 5- 100 A
IS(OFF) OFF-state
leakage
current
VCC= 5.5 V; see Figure8 [2] - 0.1 5- 200 A
IS(ON) ON-state
leakage
current
VCC= 5.5 V; see Figure9 [2] - 0.1 5- 200 A
ICC supply current VI = 5.5 Vor GND;
VSW =GNDor VCC;
VCC =1.65Vto 5.5V
[2] - 0.1 10 - 200 A
ICC additional
supply current
pin nE; VI =VCC 0.6V;
VSW =GNDor VCC;
VCC =5.5V
[2] -5 500 - 5000 A
NXP Semiconductors 74LVC2G66
Bilateral switch
[1] All typical values are measured at Tamb =25C.
[2] These typical values are measured at VCC =3.3V.
10.1 Test circuits input
capacitance
-2.0 - - - pF
CS(OFF) OFF-state
capacitance
-5.0 - - - pF
CS(ON) ON-state
capacitance
-9.5 - - - pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74LVC2G66
Bilateral switch
10.2 ON resistance
[1] Typical values are measured at Tamb= 25 C and nominal VCC.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
Table 8. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground0 V); for graphs see Figure 11 to Figure 16.
RON(peak) ON resistance
(peak) =GNDto VCC; see Figure10
ISW =4mA;
VCC =1.65Vto1.95V 34.0 130 - 195
ISW =8mA; VCC= 2.3 V to 2.7V - 12.0 30 - 45
ISW =12mA; VCC= 2.7V - 10.4 25 - 38
ISW =24mA; VCC= 3.0 V to 3.6V - 7.8 20 - 30
ISW =32mA; VCC= 4.5 V to 5.5V - 6.2 15 - 23
RON(rail) ON resistance
(rail)= GND; see Figure10
ISW =4mA;
VCC =1.65Vto1.95V
-8.2 18 - 27
ISW =8mA; VCC= 2.3 V to 2.7V - 7.1 16 - 24
ISW =12mA; VCC= 2.7V - 6.9 14 - 21
ISW =24mA; VCC= 3.0 V to 3.6V - 6.5 12 - 18
ISW =32mA; VCC= 4.5 V to 5.5V - 5.8 10 - 15 =VCC; see Figure10
ISW =4mA;
VCC =1.65Vto1.95V
-10.4 30 - 45
ISW =8mA; VCC= 2.3 V to 2.7V - 7.6 20 - 30
ISW =12mA; VCC= 2.7V - 7.0 18 - 27
ISW =24mA; VCC= 3.0 V to 3.6V - 6.1 15 - 23
ISW =32mA; VCC= 4.5 V to 5.5V - 4.9 10 - 15
RON(flat) ON resistance
(flatness) =GNDto VCC [2]
ISW =4mA;
VCC =1.65Vto1.95V
-26.0 - - -
ISW =8mA; VCC= 2.3 V to 2.7V - 5.0 - - -
ISW =12mA; VCC =2.7V - 3.5 - - -
ISW =24mA; VCC= 3.0 V to 3.6V - 2.0 - - -
ISW =32mA; VCC= 4.5 V to 5.5V - 1.5 - - -
NXP Semiconductors 74LVC2G66
Bilateral switch
10.3 ON resistance test circuit and graphs
NXP Semiconductors 74LVC2G66
Bilateral switch
NXP Semiconductors 74LVC2G66
Bilateral switch
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ {(CL +CS(ON)) VCC2 fo} where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
CS(ON)= maximum ON-state switch capacitance in pF;
VCC= supply voltage in V;
N = number of inputs switching;
Table 9. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0 V); for test circuit see Figure 19.
tpd propagation delay nYto nZ or nZto nY;
see Figure17
[2][3]
VCC= 1.65Vto 1.95V - 0.8 2.0 - 3.0 ns
VCC= 2.3Vto 2.7V - 0.4 1.2 - 2.0 ns
VCC= 2.7V - 0.4 1.0 - 1.5 ns
VCC= 3.0Vto 3.6V - 0.3 0.8 - 1.5 ns
VCC= 4.5Vto 5.5V - 0.2 0.6 - 1.0 ns
ten enable time nE to nY or nZ;
see Figure18
[4]
VCC= 1.65Vto 1.95V 1.0 4.6 10 1.0 13.0 ns
VCC= 2.3Vto 2.7V 1.0 2.7 5.6 1.0 7.5 ns
VCC= 2.7V 1.0 2.7 5.0 1.0 6.5 ns
VCC= 3.0Vto 3.6V 1.0 2.4 4.4 1.0 6.0 ns
VCC= 4.5Vto 5.5V 1.0 1.8 3.9 1.0 5.0 ns
tdis disable time nE to nY or nZ; see
Figure18
[5]
VCC= 1.65Vto 1.95V 1.0 3.8 9.0 1.0 11.5 ns
VCC= 2.3Vto 2.7V 1.0 2.1 5.5 1.0 7.0 ns
VCC= 2.7V 1.0 3.5 6.5 1.0 8.5 ns
VCC= 3.0Vto 3.6V 1.0 3.0 6.0 1.0 8.0 ns
VCC= 4.5Vto 5.5V 1.0 2.2 5.0 1.0 6.5 ns
CPD power dissipation
capacitance =50pF; fi =10MHz; =GNDto VCC
[6]
VCC= 2.5V - 9.0 - - - pF
VCC= 3.3V -11.0 -- -pF
VCC= 5.0V -15.7 -- -pF
NXP Semiconductors 74LVC2G66
Bilateral switch
{(CL +CS(ON)) VCC2 fo} = sum of the outputs.
11.1 Waveforms and test circuit
Table 10. Measurement points
1.65Vto 1.95V 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.3Vto 2.7V 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.7V 1.5V 1.5V VOL + 0.3 V VOH 0.3 V
3.0Vto 3.6V 1.5V 1.5V VOL + 0.3 V VOH 0.3 V
4.5Vto 5.5V 0.5 VCC 0.5 VCC VOL + 0.3 V VOH 0.3 V
NXP Semiconductors 74LVC2G66
Bilateral switch
Table 11. Test data
1.65 V to 1.95V VCC 2.0ns 30pF 1k open GND 2 VCC
2.3 V to 2.7V VCC 2.0ns 30pF 500 open GND 2 VCC
2.7V 2.7 V 2.5ns 50pF 500 open GND 6 V
3.0 V to 3.6V 2.7 V 2.5ns 50pF 500 open GND 6 V
4.5 V to 5.5V VCC 2.5ns 50pF 500 open GND 2 VCC
NXP Semiconductors 74LVC2G66
Bilateral switch
11.2 Additional dynamic characteristicsTable 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0 V); Tamb =25 C.
THD total harmonic distortion RL =10k; CL =50pF; fi=1 kHz; see Figure20
VCC= 1.65V - 0.032- %
VCC= 2.3V - 0.008- %
VCC= 3.0V - 0.006- %
VCC= 4.5V - 0.005- % =10k; CL =50pF; fi=10 kHz; see Figure20
VCC= 1.65V - 0.068- %
VCC= 2.3V - 0.009- %
VCC= 3.0V - 0.008- %
VCC= 4.5V - 0.006- %
f(3dB) 3 dB frequency response RL =600 ; CL=50 pF; see Figure21
VCC= 1.65V - 135 - MHz
VCC= 2.3V - 145 - MHz
VCC= 3.0V - 150 - MHz
VCC= 4.5V - 155 - MHz =50 ; CL=10 pF; see Figure21
VCC= 1.65V - 200 - MHz
VCC= 2.3V - 350 - MHz
VCC= 3.0V - 410 - MHz
VCC= 4.5V - 440 - MHz =50 ; CL=5 pF; see Figure21
VCC= 1.65V - > 500- MHz
VCC= 2.3V - > 500- MHz
VCC= 3.0V - > 500- MHz
VCC= 4.5V - > 500- MHz
iso isolation (OFF-state) RL =600 ; CL =50pF; fi=1 MHz; see Figure22
VCC =1.65V - 46 - dB
VCC =2.3V - 46 - dB
VCC =3.0V - 46 - dB
VCC =4.5V - 46 - dB =50 ; CL =5pF; fi=1 MHz; see Figure22
VCC =1.65V - 37 - dB
VCC =2.3V - 37 - dB
VCC =3.0V - 37 - dB
VCC =4.5V - 37 - dB
