74LVC273DB Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC273DB
Octal D-type flip-flop with reset; positive-edge trigger
1. General description
The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear)
all flip-flops simultaneously. The state of each Dn input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW
voltage level on the MR input.
The device is useful for applications where the true output only is required and the clock
and master reset are common to all storage elements.
2. Features and benefits Wide supply voltage range from 1.2 Vto 3.6V Inputs accept voltages up to 5.5V CMOS low power consumption Direct interface with TTL levels Output drive capability 50  transmission lines at +85C Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 C to +85 C and 40 C to +125C
74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 6 — 31 December 2012 Product data sheet
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74LVC273D 40 Cto +125C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVC273DB 40 Cto +125C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74LVC273PW 40 Cto +125C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74LVC273BQ 40 Cto +125C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 master reset input (active LOW) 11 clock input (LOW-to-HIGH; edge-triggered)
D[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input
Q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 flip-flop output
GND 10 ground (0 V)
VCC 20 supply voltage
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
 = LOW-to-HIGH clock transition
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C the value of Ptotderates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 3. Function table[1]
Reset (clear) L XXL
Load ‘1’ H  hH
Load ‘0’ H  lL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage [2] 0.5 VCC + 0.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [3]- 500 mW
Table 5. Recommended operating conditions
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage 0 - VCC V
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
9. Static characteristics
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall
rate
VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 5. Recommended operating conditions …continued
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65  VCC- - 0.65  VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35  VCC -0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V - 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; VI =5.5V orGND- 0.1 5- 20 A
ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 10 -40 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6 V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC 5.0 -- -pF
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
10. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure8.
tpd propagation
delay
CP to Qn; see Figure5 [2]
VCC = 1.2 V - 18 - - - ns
VCC = 1.65 V to 1.95 V 2.5 9.7 19.2 2.5 22.2 ns
VCC = 2.3 V to 2.7 V 1.8 4.9 9.9 1.8 11.4 ns
VCC = 2.7 V 1.5 4.5 8.4 1.5 10.5 ns
VCC = 3.0 V to 3.6 V 1.5 4.1 8.2 1.5 10.5 ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure6
VCC = 1.2 V - 18 - - - ns
VCC = 1.65 V to 1.95 V 2.4 10.2 20.4 2.4 23.5 ns
VCC = 2.3 V to 2.7 V 1.7 5.2 10.5 1.7 12.1 ns
VCC = 2.7 V 1.5 4.7 8.9 1.5 11.5 ns
VCC = 3.0 V to 3.6 V 1.5 4.3 8.7 1.5 11.0 ns pulse width clock HIGH or LOW; see Figure5
VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns
VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns
VCC = 2.7 V 5.0 1.8 - 5.0 - ns
VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns
master reset LOW; see Figure6
VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns
VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns
VCC = 2.7 V 5.0 1.7 - 5.0 - ns
VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns
trec recovery time MRto CP; see Figure6
VCC = 1.65 V to 1.95 V 2.0 - - 2.0 - ns
VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns
VCC = 2.7 V 2.0 1.0 - 2.0 - ns
VCC = 3.0 V to 3.6 V 2.0 1.0 - 2.0 - ns
tsu set-up time Dnto CP; see Figure7
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 3.5 - - 3.5 - ns
VCC = 2.7 V 3.0 1.0 - 3.0 - ns
VCC = 3.0 V to 3.6 V 1.0 0.0 - 1.0 - ns hold time Dnto CP; see Figure7
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns
VCC = 2.7 V 2.0 0.2 - 2.0 - ns
VCC = 3.0 V to 3.6 V 1.0 0.0 - 1.0 - ns
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volt= number of inputs switching
(CL VCC2fo)= sum of the outputs
11. Waveforms
fmax maximum
frequency
see Figure5
VCC = 1.65 V to 1.95 V 80 - - 64 - MHz
VCC = 2.3 V to 2.7 V 100 - - 80 - MHz
VCC = 2.7 V 150 - - 150 - MHz
VCC = 3.0 V to 3.6 V 150 230 - 150 - MHz
tsk(o) output skew time VCC= 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power dissipation
capacitance
per flip-flop; VI = GND to VCC [4]
VCC = 1.65 V to 1.95 V - 14.0 - - - pF
VCC = 2.3 V to 2.7 V - 17.7 - - - pF
VCC = 3.0 V to 3.6 V - 21.0 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure8.
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
NXP Semiconductors 74L VC273
Octal D-type flip-flop with reset; positive-edge trigger
Table 8. Measurement points
1.2V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V
1.65Vto 1.95V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V
2.3Vto 2.7V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V
2.7V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V
3.0 V to 3.6V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V
Table 9. Test data
1.2V VCC  2 ns 30pF 1 k open 2  VCC GND
1.65Vto 1.95V VCC  2 ns 30pF 1 k open 2  VCC GND
2.3Vto 2.7V VCC  2 ns 30pF 500 open 2  VCC GND
2.7V 2.7V  2.5ns 50pF 500 open 2  VCC GND
3.0Vto 3.6V 2.7V  2.5ns 50pF 500 open 2  VCC GND

Partno	Mfg	Dc	Qty	Available	Descript
74LVC273DB	PH	N/a	134	avai	Octal D-type flip-flop with reset; positive-edge trigger