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74LVC1G79GMNXPN/a148avai74LVC1G79; Single D-type flip-flop; positive edge trigger
74LVC1G79GVNXPN/a3512avai74LVC1G79; Single D-type flip-flop; positive edge trigger
74LVC1G79GWNXP/PHILIPSN/a3000avai74LVC1G79; Single D-type flip-flop; positive edge trigger


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74LVC1G79GW ,74LVC1G79; Single D-type flip-flop; positive edge triggerFEATURES DESCRIPTION• Wide supply voltage range from 1.65 V to 5.5 V The 74LVC1G79 is a high-perfor ..
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74LVC1G80GW ,Single D-type flip-flop; positive-edge trigger
74LVC1G80GW ,Single D-type flip-flop; positive-edge trigger
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74LVC1G79GM-74LVC1G79GV-74LVC1G79GW
Single D-type flip-flop; positive-edge trigger
1. General description
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition
of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Inputs can be driven from either 3.3Vor5 V devices. This feature allows the use of this
device in a mixed 3.3V and5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65Vto 5.5V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65Vto 1.95V) JESD8-5 (2.3Vto 2.7V) JESD8B/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C.
74L VC1G79
Single D-type flip-flop; positive-edge trigger
Rev. 11 — 2 July 2012 Product data sheet
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger
3. Ordering information

4. Marking

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram

Table 1. Ordering information

74LVC1G79GW 40 Cto+125C TSSOP5 plastic thin shrink small outline package; leads; body width 1.25 mm
SOT353-1
74LVC1G79GV 40 Cto+125C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G79GM 40 Cto+125C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body1 1.45 0.5 mm
SOT886
74LVC1G79GF 40 C to +125 C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body 11 0.5 mm
SOT891
74LVC1G79GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC1G79GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
74LVC1G79GX 40 C to +125C X2SON5 X2SON5: plastic thermal enhanced extremely
thin small outline package; no leads; 5
terminals; body 0.8 0.8 0.35 mm
SOT1226
Table 2. Marking codes

74LVC1G79GW VP
74LVC1G79GV V79
74LVC1G79GM VP
74LVC1G79GF VP
74LVC1G79GN VP
74LVC1G79GS VP
74LVC1G79GX VP
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger

6. Pinning information
6.1 Pinning

NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger
6.2 Pin description

7. Functional description

[1] H = HIGH voltage level;
L = LOW voltage level;
 = LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
Table 3. Pin description
1 1 data input 2 2 clock pulse input
GND 3 3 ground (0 V) 4 4 data output
n.c. - 5 not connected
VCC 5 6 supply voltage
Table 4. Function table[1]
LL HH q
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger
8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 250 mW
Tstg storage temperature 65 +150 C
Table 6. Recommended operating conditions

VCC supply voltage 1.65 - 5.5 V input voltage 0 - 5.5 V output voltage Active mode 0 - VCC V
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
Tamb=
40 C to +85C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
VOH HIGH-level output voltage VI =VIHorVIL= 100 A; VCC = 1.65 V to 5.5V VCC 0.1 - - V= 4mA; VCC = 1.65V 1.2 - - V= 8mA; VCC = 2.3V 1.9 - - V= 12 mA; VCC = 2.7 V 2.2 - - V= 24 mA; VCC = 3.0 V 2.3 - - V= 32 mA; VCC = 4.5 V 3.8 - - V
VOL LOW-level output voltage VI =VIHorVIL =100 A; VCC = 1.65 V to 5.5 V - - 0.1 V =4mA; VCC = 1.65V - - 0.45 V =8mA; VCC = 2.3V - - 0.3 V =12mA; VCC = 2.7 V - - 0.4 V =24mA; VCC = 3.0 V - - 0.55 V =32mA; VCC = 4.5 V - - 0.55 V input leakage current VI= 5.5Vor GND; VCC =0Vto5.5V - 0.1 5 A
IOFF power-off leakage current VCC = 0 V; VIorVO =5.5V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC =1.65Vto5.5V; IO =0A
-0.1 10 A
ICC additional supply current per pin; VCC = 2.3 V to 5.5V; =VCC 0.6 V; IO =0A 500 A input capacitance VCC= 3.3 V; VI = GND to VCC -5 - pF
Tamb=
40 C to +125C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7  VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3  VCC V
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger

[1] All typical values are measured at VCC=3.3 V and Tamb =25C.
11. Dynamic characteristics

VOH HIGH-level output voltage VI =VIHorVIL= 100 A; VCC = 1.65 V to 5.5V VCC 0.1 - - V= 4mA; VCC = 1.65V 0.95 - - V= 8mA; VCC = 2.3V 1.7 - - V= 12 mA; VCC = 2.7 V 1.9 - - V= 24 mA; VCC = 3.0 V 2.0 - - V= 32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI =VIHorVIL =100 A; VCC = 1.65 V to 5.5 V - - 0.1 V =4mA; VCC = 1.65V - - 0.70 V =8mA; VCC = 2.3V - - 0.45 V =12mA; VCC = 2.7 V - - 0.60 V =24mA; VCC = 3.0 V - - 0.80 V =32mA; VCC = 4.5 V - - 0.80 V input leakage current VI= 5.5Vor GND; VCC =0Vto5.5V - - 100 A
IOFF power-off leakage current VCC = 0 V; VIorVO =5.5V - - 200 A
ICC supply current VI= 5.5Vor GND;
VCC =1.65Vto5.5V; IO =0A 200 A
ICC additional supply current per pin; VCC = 2.3 V to 5.5V; =VCC 0.6 V; IO =0A - 5000 A
Table 7. Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground=0V).
Table 8. Dynamic characteristics

Voltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
tpd propagation delay CPto Q; see Figure8 [2]
VCC = 1.65 V to 1.95 V 1.0 3.6 9.9 1.0 12.5 ns
VCC = 2.3 V to 2.7 V 0.5 2.3 7.0 0.5 9.0 ns
VCC = 2.7 V 0.5 2.6 6.0 0.5 8.0 ns
VCC = 3.0 V to 3.6 V 0.5 2.2 5.0 0.5 6.5 ns
VCC = 4.5 V to 5.5 V 0.5 1.7 3.8 0.5 5.0 ns
tsu set-up time Dto CP; see Figure9
VCC = 1.65 V to 1.95 V 2.5 1.4 - 2.5 - ns
VCC = 2.3 V to 2.7 V 1.7 0.9 - 1.7 - ns
VCC = 2.7 V 1.7 0.9 - 1.7 - ns
VCC = 3.0 V to 3.6 V 1.3 0.6 - 1.2 - ns
VCC = 4.5 V to 5.5 V 1.2 0.6 - 1.2 - ns
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger

[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs. hold time Dto CP; see Figure9
VCC = 1.65 V to 1.95 V 0 0.7 - 0 - ns
VCC = 2.3 V to 2.7 V 0 0.4 - 0 - ns
VCC = 2.7 V +0.5 0.3 - 0.5 - ns
VCC = 3.0 V to 3.6 V +0.5 0.3 - 0.5 - ns
VCC = 4.5 V to 5.5 V +0.5 0.2 - 0.5 - ns pulse width CP HIGH or LOW;
see Figure9
VCC = 1.65 V to 1.95 V 3.0 1.1 - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 0.7 - 2.5 - ns
VCC = 2.7 V 2.5 0.6 - 2.5 - ns
VCC = 3.0 V to 3.6 V 2.5 0.6 - 2.5 - ns
VCC = 4.5 V to 5.5 V 2.0 0.5 - 2.0 - ns
fmax maximum
frequency
CP; see Figure9
VCC = 1.65 V to 1.95 V 160 250 - 160 - MHz
VCC = 2.3 V to 2.7 V 160 300 - 160 - MHz
VCC = 2.7 V 160 350 - 160 - MHz
VCC = 3.0 V to 3.6 V 160 450 - 160 - MHz
VCC = 4.5 V to 5.5 V 200 500 - 200 - MHz
CPD power dissipation
capacitance
VI = GND to VCC;
VCC= 3.3 V
[3] - 17 --- pF
Table 8. Dynamic characteristics …continued

Voltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger
12. Waveforms

NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger

Table 9. Measurement points

1.65 V to 1.95V 0.5 VCC 0.5 VCC
2.3 V to 2.7V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5V 0.5 VCC 0.5 VCC
Table 10. Test data

1.65 V to 1.95V VCC  2.0ns 30pF 1k open
2.3 V to 2.7V VCC  2.0ns 30pF 500 open
2.7V 2.7V  2.5ns 50pF 500 open
3.0V to 3.6V 2.7V  2.5ns 50pF 500 open
4.5 V to 5.5V VCC  2.5ns 50pF 500 open
NXP Semiconductors 74LVC1G79
Single D-type flip-flop; positive-edge trigger
13. Package outline

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