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74LVC163BQNXPN/a2450avai74LVC163; Presettable synchronous 4-bit binary counter; synchronous reset
74LVC163DBNXPLIPSN/a13368avaiPresettable synchronous 4-bit binary counter; synchronous reset
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74LVC163BQ-74LVC163DB-74LVC163PW
Presettable synchronous 4-bit binary counter; synchronous reset
1. General description
The 74LVC163 is a synchronous presettable binary counter which features an internal
look-ahead carry and can be used for high-speed counting. Synchronous operation is
provided by having all flip-flops clocked simultaneously on the positive-going edge of the
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter
on the positive-going edge of the clock (provided that the set-up and hold time
requirements for PE are met). Preset takes place regardless of the levels at count enable
inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all four
outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going
transition on the clock input (pin CP) (provided that the set-up and hold time requirements
for PE are met). This action occurs regardless of the levels at input pins PE, CET and
CEP. This synchronous reset feature enables the designer to modify the maximum count
with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs
(pin CEP and CET) must be HIGH in count. The CET input is fed forward to enable the
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be
used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by tPHL
2. Features and benefits
Wide supply voltage range from 1.2Vto 3.6V Inputs accept voltages up to 5.5V CMOS low power consumption Direct interface with TTL levels Synchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V)
74L VC163
Presettable synchronous 4-bit binary counter; synchronous
reset
Rev. 6 — 20 November 2012 Product data sheet
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset
JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 C to +85 C and 40 C to 125C
3. Ordering information

4. Functional diagram

Table 1. Ordering information

74LVC163D 40 Cto +125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LVC163DB 40 Cto +125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LVC163PW 40 Cto +125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74LVC163BQ 40 Cto +125C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset

NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset
5. Pinning information
5.1 Pinning

5.2 Pin description

Table 2. Pin description
1 synchronous master reset (active LOW) 2 clock input (LOW-to-HIGH, edge-triggered)
D[0:3] 3, 4, 5, 6 data input
CEP 7 count enable input
GND 8 ground (0) 9 parallel enable input (active LOW)
CET 10 count enable carry input
Q[0:3] 14, 13, 12, 11 flip-flop output 15 terminal count output
VCC 16 supply voltage
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset
6. Functional description

[1] * = the TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
X = don’t care
 = LOW-to-HIGH clock transition
7. Limiting values

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Functional table[1]

Reset (clear)l  XXX XL L
Parallel loadh  XXl l L L  XXl h H *
Count h  hhh X count *
Hold
(do nothing) l X h X qn * X l h X qn L
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage [2] 0.5 VCC + 0.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [3] -500 mW
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset
8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65  VCC- - 0.65  VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35  VCC -0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V - 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; VI =5.5V orGND- 0.1 5- 20 A
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset

[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics

ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 10 -40 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6 V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC 5.0 -- -pF
Table 6. Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics

Voltages are referenced to GND (ground=0 V). For test circuit see Figure 14.
tpd propagation delay CP to Qn; see Figure9 [2]
VCC = 1.2 V - 18 - - - ns
VCC = 1.65 V to 1.95 V 1.5 7.4 14.5 1.5 16.7 ns
VCC = 2.3 V to 2.7 V 2.6 4.2 8.1 2.6 9.4 ns
VCC = 2.7V 1.5 4.0 7.3 1.5 9.5 ns
VCC = 3.0 V to 3.6V 1.5 3.8 7.3 1.5 9.5 ns
CP to TC; see Figure9 [2]
VCC = 1.2 V - 23 - - - ns
VCC = 1.65 V to 1.95 V 1.9 8.5 15.7 1.9 18.1 ns
VCC = 2.3 V to 2.7 V 3.0 4.8 8.8 3.0 10.2 ns
VCC = 2.7V 1.5 4.6 8.1 1.5 10.5 ns
VCC = 3.0 V to 3.6V 1.5 4.3 7.9 1.5 10.0 ns
CET to TC; see Figure10 [2]
VCC = 1.2 V - 16 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.3 12.7 1.5 14.6 ns
VCC = 2.3 V to 2.7 V 2.3 3.6 7.1 2.3 8.2 ns
VCC = 2.7V 1.5 3.9 6.9 1.5 9.0 ns
VCC = 3.0 V to 3.6V 1.5 3.3 6.4 1.5 8.0 ns pulse width clock HIGH or LOW; see Figure9
VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns
VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns
VCC = 2.7 V 5.0 - - 5.0 - ns
VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset

[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in V= number of inputs switching2
tsu set-up time Dn to CP; see Figure12
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.0 - - 3.0 - ns
VCC = 3.0 V to 3.6 V 2.5 1.0 - 2.5 - ns
MR, PE to CP; see Figure12
VCC = 1.65 V to 1.95 V 4.5 - - 4.5 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.5 - - 3.5 - ns
VCC = 3.0 V to 3.6 V 3.0 1.2 - 3.0 - ns
CEP, CET to CP; see Figure13
VCC = 1.65 V to 1.95 V 8.5 - - 8.5 - ns
VCC = 2.3 V to 2.7 V 6.5 - - 6.5 - ns
VCC = 2.7 V 5.5 - - 5.5 - ns
VCC = 3.0 V to 3.6 V 5.0 2.1 - 5.0 - ns hold time Dn, PE, CEP, CET to CP; see
Figure 12 and 13
VCC = 1.65 V to 1.95 V 2.0 - - 2.0 - ns
VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns
VCC = 2.7 V 0.0 - - 0.0 - ns
VCC = 3.0 V to 3.6 V 0.5 0.0 - 0.5 - ns
fmax maximum
frequency
see Figure9
VCC = 1.65 V to 1.95 V 100 - - 80 - ns
VCC = 2.3 V to 2.7 V 125 - - 100 - ns
VCC = 2.7 V 150 - - 120 - MHz
VCC = 3.0 V to 3.6 V 150 200 - 120 - MHz
tsk(o) output skew time VCC= 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power dissipation
capacitance
per input; VI = GND to VCC [4]
VCC = 1.65 V to 1.95 V - 9.8 - - - pF
VCC = 2.3 V to 2.7 V - 13.4 - - - pF
VCC = 3.0 V to 3.6 V - 16.6 - - - pF
Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground=0 V). For test circuit see Figure 14.
NXP Semiconductors 74L VC163
Presettable synchronous 4-bit binary counter; synchronous reset
11. AC waveforms

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