74LVC109D-74LVC109PW Fast Delivery |IC PHOENIX CO.,LIMITED

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74LVC109D-74LVC109PW
Dual JK(not) flip-flop with set and reset; positive-edge trigger
1. General description
The 74LVC109A is a dual positive edge triggered JK flip-flop featuring: individual J and K inputs clock (CP) inputs set (SD) and reset (RD) inputs complementary Q and Q outputs
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input.
The J and K inputs control the state changes of the flip-flops as described in the mode
select function table. The J and K inputs must be stable one set-up time before the
LOW-to-HIGH clock transition for predictable operation. The JK design allows operation
as a D-type flip-flop by tying the J and K inputs together.
Schmitt trigger action in the clock input makes the circuit highly tolerant of slower clock
rise and fall times.
2. Features and benefits5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 C to +85 C and 40 C to +125C
74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
Rev. 5 — 29 November 2012 Product data sheet
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
3. Ordering information
4. Functional diagram
Table 1. Ordering information
All types are specified from 40  C to +125 C.
74LVC109D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LVC109DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74LVC109PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
1RD 1 asynchronous reset input (active LOW) 2 synchronous input 3 synchronous input
1CP 4 clock input (LOW-to-HIGH; edge-triggered)
1SD 5 asynchronous set input (active LOW) 6 true flip-flop output 7 complement flip-flop output
GND 8 ground (0V) 9 complement flip-flop output 10 true flip-flop output
2SD 11 asynchronous set input (active LOW)
2CP 12 clock input (LOW-to-HIGH; edge-triggered) 13 synchronous input 14 synchronous input
2RD 15 asynchronous reset input (active LOW)
VCC 16 supply voltage
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
6. Functional description
[1] H= HIGH voltage level= HIGH voltage level one set-up time before the LOW-to-HIGH CP transition= LOW voltage level= LOW voltage level one set-up time before the LOW-to-HIGH CP transition= lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition= don’t care= LOW-to-HIGH CP transition
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function selection[1]
Asynchronous set L H X X X H L
Asynchronous reset H L X X X L H
Undetermined L L X X X H H
Toggle H H  hl q q
Load 0 (reset) H H  ll L H
Load 1 (set) H H  hh H L
Hold no change H H  lh q q
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage [2] 0.5 VCC + 0.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb= 40 Cto+125C [3]- 500 mW
Tstg storage temperature 65 +150 C
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65  VCC- - 0.65  VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35  VCC -0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V - 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; VI =5.5V orGND- 0.1 5- 20 A
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 10 -40 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6 V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC 5.0 -- -pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure7.
tpd propagation
delay
nCPto nQ, nQ; see Figure5 [2]
VCC = 1.2 V - 15 - - - ns
VCC = 1.65 V to 1.95 V 1.7 6.8 15.0 1.7 17.4 ns
VCC = 2.3 V to 2.7 V 2.7 3.9 8.1 2.7 9.4 ns
VCC = 2.7 V 1.5 3.9 7.3 1.5 9.5 ns
VCC = 3.0 V to 3.6 V 1.0 3.5 6.8 1.0 8.5 ns
tPLH LOW to
HIGH
propagation
delay
nSD, nRDto nQ, nQ; see Figure6
VCC = 1.2 V - 16 - - - ns
VCC = 1.65 V to 1.95 V 1.0 6.2 15.6 1.0 18.0 ns
VCC = 2.3 V to 2.7 V 1.5 3.6 8.3 1.5 9.7 ns
VCC = 2.7 V 1.5 4.5 8.2 1.5 10.5 ns
VCC = 3.0 V to 3.6 V 1.0 3.3 7.0 1.0 9.0 ns
tPHL HIGH to
LOW
propagation
delay
nSD, nRDto nQ, nQ; see Figure6
VCC = 1.2 V - 13 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.7 14.4 1.5 16.7 ns
VCC = 2.3 V to 2.7 V 2.0 3.8 7.7 2.0 9.0 ns
VCC = 2.7 V 1.5 4.1 7.1 1.5 9.0 ns
VCC = 3.0 V to 3.6 V 1.0 3.5 6.5 1.0 8.5 ns
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. pulse width clock HIGH or LOW; see Figure5
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.3 - - 3.3 - ns
VCC = 3.0 V to 3.6 V 3.3 2.0 - 3.3 - ns
set or reset HIGH or LOW; see Figure6
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.0 - - 3.0 - ns
VCC = 3.0 V to 3.6 V 3.0 - - 3.0 - ns
trec recovery
time
nSD, nRDto nCP; see Figure6
VCC = 1.65 V to 1.95 V 5.5 - - 5.5 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.2 - - 3.2 - ns
VCC = 3.0 V to 3.6 V 3.0 - - 3.0 - ns
tsu set-up time nJ and nKto CP; see Figure5
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 3.5 - - 3.5 - ns
VCC = 2.7 V 2.7 - - 2.7 - ns
VCC = 3.0 V to 3.6 V 2.5 - - 2.5 - ns hold time nJ and nKto nCP; see Figure5
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns
VCC = 2.7 V 2.2 - - 2.2 - ns
VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - ns
fmax maximum
frequency
see Figure5
VCC = 1.65 V to 1.95 V 100 - - 80 - MHz
VCC = 2.3 V to 2.7 V 125 - - 100 - MHz
VCC = 2.7 V 150 - - 120 - MHz
VCC = 3.0 V to 3.6 V 150 330 - 120 - MHz
tsk(o) output skew
time
VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power
dissipation
capacitance =GNDto VCC [4]
VCC = 1.65 V to 1.95 V - 11.4 - - - pF
VCC = 2.3 V to 2.7 V - 17.6 - - - pF
VCC = 3.0 V to 3.6 V - 23.1 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure7.
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs
11. AC waveforms
NXP Semiconductors 74L VC109
Dual JK flip-flop with set and reset; positive-edge trigger
Table 8. Measurement points
1.2V VCC 0.5  VCC 0.5  VCC
1.65Vto 1.95V VCC 0.5  VCC 0.5  VCC
2.3Vto 2.7V VCC 0.5  VCC 0.5  VCC
2.7V 2.7 V 1.5 V 1.5 V
3.0 V to 3.6V 2.7 V 1.5 V 1.5 V

Partno	Mfg	Dc	Qty	Available	Descript
74LVC109D	NXPLIPS	N/a	13368	avai	Dual JK(not) flip-flop with set and reset; positive-edge trigger
74LVC109PW	NXP	N/a	2380	avai	Dual JK(not) flip-flop with set and reset; positive-edge trigger