74LV4094D-74LV4094N Fast Delivery |IC PHOENIX CO.,LIMITED

74LV4094N ,8-stage shift-and-store bus registerGeneral descriptionThe 74LV4094 is a low voltage Si-gate CMOS device and is pin and functional comp ..
74LV4094PW ,74LV4094; 8-stage shift-and-store bus registerApplications:number of 74LV4094 devices. Data is available at QS on the1positive-going clock edges ..
74LV4799D ,Timer for NiCd and NiMH chargers
74LV541 ,Octal buffer/line driver (3-State)
74LV541 ,Octal buffer/line driver (3-State)
74LV541N ,Octal buffer/line driver 3-StateFEATURES DESCRIPTIONThe 74LV541 is a low–voltage CMOS device and is pin and function• Optimized fo ..
7WBD3125USG , 2-Bit Translating Bus Switch
8.192 , 64-Pin 8-Bit Flash Microcontroller Product Brief
8.192 , 64-Pin 8-Bit Flash Microcontroller Product Brief
80021012A ,Octal Bus Transceivers With 3-State OutputsLogic Diagram (Positive Logic)1DIR19OE2A118B1To Seven Other ChannelsCopyright 2016, Texas Instrume ..
8035AHL , HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
8041-05-011 , DIP Reed Relays

74LV4094D-74LV4094N
8-stage shift-and-store bus register
1. General description
The 74LV4094 is a low voltage Si-gate CMOS device and is pin and functional compatible
with 74HC4094; 74HCT4094.
The 74LV4094 is an 8-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input to parallel buffered 3-state outputs
QP0to QP7. The parallel outputs may be connected directly to common bus lines. Data is
shifted on positive-going clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR) input is HIGH. Data in the
storage register appears at the outputs whenever the output enable (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094
devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed
operation in cascaded systems with a fast clock rise time. The same serial data is
available at QS2 on the next negative going clock edge. This is used for cascading
74LV4094 devices when the clock has a slow rise time.
2. Features and benefits Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb= 25 C ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125C
3. Applications Serial-to-parallel data conversion Remote control holding register
74L V4094
8-stage shift-and-store bus register
Rev. 4 — 19 December 2011 Product data sheet
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
4. Ordering information
5. Functional diagram
Table 1. Ordering information
74LV4094N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV4094D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9
SOT109-1
74LV4094DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LV4094PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description
STR 1 strobe input 2 data input 3 clock input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
VSS 8 ground supply voltage
QS1, QS2 9,10 serial output 15 output enable input
VDD 16 supply voltage
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
7. Functional description
[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
 = positive-going transition;  = negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Table 3. Function table[1] L XXZ Z Q6S NC L XXZ Z NC Q7S HL X NC NC Q6S NC HH L L QPn 1Q6S NC H HHH QPn 1Q6S NC H H H NC NCNCQ7S
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60C.
9. Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC=1.0 V (with input levels GND or VCC).
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 50 mA output current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C
DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW
(T)SSOP16 package [3]- 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage [1] 1.03.3 3.6V input voltage 0 - VCC V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
10. Static characteristics
[1] All typical values are measured at Tamb = 25 C.
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC = 1.2 V VCC 0.6 - VCC -V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - 0.4 GND - GND V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; all pins
IO = 100 A; VCC = 1.2 V - 1.2 - - - V
IO = 100 A; VCC = 2.0 V 1.8 2.0 - 1.8 - V
IO = 100 A; VCC = 2.7 V 2.5 2.7 - 2.5 - V
IO = 100 A; VCC = 3.0 V 2.8 3.0 - 2.8 - V
VI = VIH or VIL; pins QPn
IO = 6 mA; VCC = 3.0 V 2.40 2.82- 2.20 - V
VOL LOW-level
output voltage
VI = VIH or VIL; all pins
IO = 100 A; VCC = 1.2 V - 0 - - - V
IO = 100 A; VCC = 2.0 V - 0 0.2 - 0.2 V
IO = 100 A; VCC = 2.7 V - 0 0.2 - 0.2 V
IO = 100 A; VCC = 3.0 V - 0 0.2 - 0.2 V
VI = VIH or VIL; pins QPn
IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V input leakage
current =VCCor GND; VCC =3.6V - - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; VO =VCCor GND;
VCC =3.6V 5.0 - 10.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =3.6V - 20.0 - 160 A
ICC additional supply
current
per input; VI = VCC  0.6 V;
VCC= 2.7 V to 3.6 V - 500.0 - 850 A input capacitance - 3.5 - pF
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
11. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
tpd propagation
delay
CP to QS1; see Figure8 [3]
VCC = 1.2 V - 90 - - - ns
VCC = 2.0 V - 31 58 - 70 ns
VCC = 2.7 V - 23 43 - 51 ns
VCC = 3.0 V to 3.6 V [2] -17 34 - 41 ns
VCC = 3.3 V; CL = 15 pF - 14 - - - ns
CP to QS2; see Figure8 [3]
VCC = 1.2 V - 80 - - - ns
VCC = 2.0 V - 27 51 - 61 ns
VCC = 2.7 V - 20 38 - 45 ns
VCC = 3.0 V to 3.6 V - 14 30 - 36 ns
VCC = 3.3 V; CL = 15 pF [2] -13 - - - ns
CP to QPn; see Figure8 [3]
VCC = 1.2 V - 115 - - - ns
VCC = 2.0 V - 39 75 - 90 ns
VCC = 2.7 V - 29 55 - 66 ns
VCC = 3.0 V to 3.6 V [2] -22 44 - 53 ns
VCC = 3.3 V; CL = 15 pF - 18 - - - ns
STR to QPn; see Figure9 [3]
VCC = 1.2 V - 105 - - - ns
VCC = 2.0 V - 36 68 - 82 ns
VCC = 2.7 V - 26 50 - 60 ns
VCC = 3.0 V to 3.6 V [2] -20 40 - 48 ns
VCC = 3.3 V; CL = 15 pF - 17 - - - ns
ten enable time OE to QPn; see Figure11 [4]
VCC = 1.2 V - 100 - - - ns
VCC = 2.0 V - 34 65 - 77 ns
VCC = 2.7 V - 25 48 - 56 ns
VCC = 3.0 V to 3.6 V [2] -19 38 - 45 ns
tdis disable time OE to QPn; see Figure11 [5]
VCC = 1.2 V - 65 - - - ns
VCC = 2.0 V - 24 40 - 49 ns
VCC = 2.7 V - 18 32 - 37 ns
VCC = 3.0 V to 3.6 V [2] -14 26 - 30 ns
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register pulse width CP HIGH or LOW; see Figure8
VCC = 2.0 V 34 9 - 41 - ns
VCC = 2.7 V 25 6 - 30 - ns
VCC = 3.0 V to 3.6 V [2] 20 5 - 24 - ns
STR HIGH; see Figure9
VCC = 2.0 V 34 9 - 41 - ns
VCC = 2.7 V 25 6 - 30 - ns
VCC = 3.0 V to 3.6 V [2] 20 5 - 24 - ns
tsu set-up time D to CP; see Figure10
VCC = 1.2 V - 25 - - - ns
VCC = 2.0 V 22 9 - 26 - ns
VCC = 2.7 V 16 6 - 19 - ns
VCC = 3.0 V to 3.6 V [2] 13 5 - 15 - ns
CP to STR; see Figure9
VCC = 1.2 V - 50 - - - ns
VCC = 2.0 V 43 17 - 51 - ns
VCC = 2.7 V 31 13 - 38 - ns
VCC = 3.0 V to 3.6 V [2] 25 10 - 30 - ns hold time D to CP; see Figure10
VCC = 1.2 V - 10 - - - ns
VCC = 2.0 V 5 4- +5 - ns
VCC = 2.7 V 5 3- +5 - ns
VCC = 3.0 V to 3.6 V [2] 5 2- +5 - ns
CP to STR; see Figure9
VCC = 1.2 V - 25 - - - ns
VCC = 2.0 V 5 9- +5 - ns
VCC = 2.7 V 5 6- +5 - ns
VCC = 3.0 V to 3.6 V [2] 5 5- +5 - ns
fmax maximum
frequency
CP; see Figure8
VCC = 2.0 V 14 52 - 12 - MHz
VCC = 2.7 V 19 70 - 16 - MHz
VCC = 3.0 V to 3.6 V 24 87 - 20 - MHz
VCC = 3.3 V; CL = 15 pF [2] -95 - - - MHz
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
NXP Semiconductors 74LV4094
8-stage shift-and-store bus register
[1] All typical values are measured at Tamb = 25 C.
[2] All typical values are measured at VCC =3.3V.
[3] tpd is the same as tPLH and tPHL.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPLZ and tPHZ.
[6] tt is the same as tTHL and tTLH.
[7] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
12. Waveforms
CPD power
dissipation
capacitance =50pF;f=1 MHz; =GNDto VCC
[7] -83 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

Partno	Mfg	Dc	Qty	Available	Descript
74LV4094D	NXP	N/a	650	avai	8-stage shift-and-store bus register
74LV4094N	NXP	N/a	825	avai	8-stage shift-and-store bus register