74LV4053D ,Triple 2-channel analog multiplexer/demultiplexer74LV4053Triple single-pole double-throw analog switchRev. 04 — 10 August 2009 Product data sheet1.
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74LV4053D-74LV4053DB-74LV4053PW
Triple 2-channel analog multiplexer/demultiplexer
General descriptionThe 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device
andis pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has
a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all
switches into the high-impedance OFF-state, independent of Sn.
VCC and GND are the supply voltage connectionsfor the digital control inputs (Sn and E).
The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not
exceed6V. For operationasa digital multiplexer/demultiplexer, VEEis connectedto GND
(typically ground). VEE and VSS are the supply voltage connections for the switches.
Features Optimized for low-voltage applications: 1.0 V to 3.6V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6V Low ON resistance: 180 Ω (typical) at VCC − VEE= 2.0 V 100 Ω (typical) at VCC − VEE= 3.0 V 75 Ω (typical) at VCC − VEE= 4.5 V Logic level translation: To enable 3 V logic to communicate with ±3 V analog signals Typical ‘break before make’ built in ESD protection: HBM JESD22-A114-C exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from −40 °Cto+85 °C and from −40°Cto +125°C
74L V4053
Triple single-pole double-throw analog switch
Rev. 04 — 10 August 2009 Product data sheet
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch Ordering information Functional diagram
Table 1. Ordering information74LV4053N −40 °C to +125°C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV4053D −40 °C to +125°C SO16 plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74LV4053DB −40 °C to +125°C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
74LV4053PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74LV4053BQ −40 °C to +125°C DHVQFN16 plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5× 3.5 × 0.85 mm
SOT763-1
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 6 enable input (active LOW)
VEE 7 supply voltage
GND 8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output
1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output
1Z, 2Z, 3Z 14, 15, 4 common output or input
VCC 16 supply voltage
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch Functional description[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Limiting values[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2] The minimum input voltage rating may be exceeded if the input current rating is observed.
[3] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table[1] L nY0 to nZ H nY1 to nZ X switches off
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
VCC supply voltage [1] −0.5 +7.0 V
IIK input clamping current VI< −0.5 V or VI > VCC + 0.5V [2]- ±20 mA
ISK switch clamping current VSW< −0.5 V or VSW > VCC + 0.5V [2]- ±20 mA
ISW switch current VSW> −0.5 VorVSW
sourceor sink current
[2]- ±25 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C [3]
DIP16 package - 750 mW
SO16 package - 500 mW
TSSOP16 package - 500 mW
DHVQFN16 package - 500 mW
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch Recommended operating conditions
[1] The static characteristicsare guaranteed from VCC=1.2Vto6.0V,butLV devicesare guaranteedto function downto VCC=1.0V (with
input levels GND or VCC).
Table 5. Recommended operating conditions
VCC supply voltage see Figure8 1 3.3 6 V input voltage 0 - VCC V
VSW switch voltage 0 - VCC V
Tamb ambient temperature in free air −40 - +125 °C
Δt/ΔV input transition rise and fall rate VCC= 1.0 V to 2.0V - - 500 ns/V
VCC= 2.0 V to 2.7V - - 200 ns/V
VCC= 2.7 V to 3.6V - - 100 ns/V
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch Static characteristics
[1] Typical values are measured at Tamb = 25°C.
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V 3.15 - - 3.15 - V
VCC = 6.0 V 4.20 - - 4.20 - V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V - - 1.35 - 1.35 V
VCC = 6.0 V - - 1.80 - 1.80 V input leakage current VI =VCCor GND
VCC= 3.6V - - 1.0 - 1.0 μA
VCC= 6.0V - - 2.0 - 2.0 μA
IS(OFF) OFF-state leakage current VI = VIH or VIL; see Figure9
VCC = 3.6V - - 1.0 - 1.0 μA
VCC = 6.0V - - 2.0 - 2.0 μA
IS(ON) ON-state leakage current VI = VIH or VIL; see Figure10
VCC = 3.6V - - 1.0 - 1.0 μA
VCC = 6.0V - - 2.0 - 2.0 μA
ICC supply current VI = VCC or GND; IO = 0A
VCC = 3.6V - - 20 - 40 μA
VCC = 6.0V - - 40 - 80 μA
ΔICC additional supply current per input; VI = VCC − 0.6V;
VCC= 2.7Vto 3.6V - 500 - 850 μA input capacitance - 3.5 - - - pF
Csw switch capacitance independent pins nYn - 5 - - - pF
common pins nZ - 8 - - - pF
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch
9.1 Test circuits
9.2 ON resistance
Table 7. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
RON(peak) ON resistance (peak) VI = 0 V to VCC − VEE
VCC= 1.2 V; ISW= 100μA [2] -- - - - Ω
VCC= 2.0V; ISW= 1000μA - 180 365 - 435 Ω
VCC= 2.7V; ISW= 1000μA - 115 225 - 270 Ω
VCC= 3.0 V to 3.6 V;
ISW= 1000μA 100 200 - 245 Ω
VCC= 4.5V; ISW= 1000μA - 75 150 - 180 Ω
VCC= 6.0V; ISW= 1000μA - 70 140 - 165 Ω
ΔRON ONresistance mismatch
between channels
VI = 0 V to VCC − VEE
VCC= 1.2 V; ISW= 100μA [2] -- - - - Ω
VCC= 2.0V; ISW= 1000 μA- 5 - - - Ω
VCC= 2.7V; ISW= 1000 μA- 4 - - - Ω
VCC= 3.0 V to 3.6 V;
ISW= 1000μA - - - Ω
VCC= 4.5V; ISW= 1000 μA- 3 - - - Ω
VCC= 6.0V; ISW= 1000 μA- 2 - - - Ω
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch
[1] Typical values are measured at Tamb =25°C.
[2] When supply voltages (VCC− VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
1.2 V, it is recommended to use these devices only for transmitting digital signals.
RON(rail) ON resistance (rail) VI = GND
VCC= 1.2 V; ISW= 100μA [2] - 250 - - - Ω
VCC= 2.0V; ISW= 1000μA - 120 280 - 325 Ω
VCC= 2.7V; ISW= 1000μA - 75 170 - 195 Ω
VCC= 3.0 V to 3.6 V;
ISW= 1000μA 70 155 - 180 Ω
VCC= 4.5V; ISW= 1000μA - 50 120 - 135 Ω
VCC= 6.0V; ISW= 1000μA - 45 105 - 120 Ω
RON(rail) ON resistance (rail) VI = VCC − VEE
VCC= 1.2 V; ISW= 100μA [2] - 350 - - - Ω
VCC= 2.0V; ISW= 1000μA - 170 340 - 400 Ω
VCC= 2.7V; ISW= 1000μA - 105 210 - 250 Ω
VCC= 3.0 V to 3.6 V;
ISW= 1000μA 95 190 - 225 Ω
VCC= 4.5V; ISW= 1000μA - 70 140 - 165 Ω
VCC= 6.0V; ISW= 1000μA - 65 125 - 150 Ω
Table 7. ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch
9.3 On resistance waveform and test circuit
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 15.
tpd propagation delay nYn, nZ to nZ, nYn; see Figure13 [2]
VCC= 1.2V - 25 - - - ns
VCC= 2.0V - 9 17 - 20 ns
VCC= 2.7V - 6 13 - 15 ns
VCC= 3.0 V to 3.6 V [3] - 5 10 - 12 ns
VCC= 4.5V - 4 9 - 10 ns
VCC= 6.0V - 3 7 - 8 ns
ten enable time Eto nYn, nZ; see Figure14 [2]
VCC= 1.2V - 100 - - - ns
VCC= 2.0V - 34 65 - 77 ns
VCC= 2.7V - 25 48 - 56 ns
VCC= 3.0Vto 3.6V;CL =15pF[3] -16 - - - ns
VCC= 3.0 V to 3.6 V [3] - 19 38 - 45 ns
VCC= 4.5V - 17 32 - 38 ns
VCC= 6.0V - 13 25 - 29 ns
Sn to nYn, nZ; see Figure14 [2]
VCC= 1.2V - 125 - - - ns
VCC= 2.0V - 43 82 - 97 ns
VCC= 2.7V - 31 60 - 71 ns
VCC= 3.0Vto 3.6V;CL =15pF[3] -20 - - - ns
VCC= 3.0 V to 3.6 V [3] - 24 48 - 57 ns
VCC= 4.5V - 21 41 - 48 ns
VCC= 6.0V - 16 31 - 37 ns
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch
[1] All typical values are measured at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3V).
[4] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ((CL + CSW) × VCC2×fo) where: = input frequency in MHz, fo= output frequency in MHz= output load capacitance inpF
CSW= maximum switch capacitance in pF;
VCC= supply voltage in Volts= number of inputs switching
Σ(CL× VCC2×fo)= sum of the outputs.
tdis disable time Eto nYn, nZ; see Figure14 [2]
VCC= 1.2V - 95 - - - ns
VCC= 2.0V - 34 61 - 73 ns
VCC= 2.7V - 26 46 - 54 ns
VCC= 3.0Vto 3.6V;CL =15pF[3] -17 - - - ns
VCC= 3.0 V to 3.6 V [3] - 20 37 - 44 ns
VCC= 4.5V - 18 32 - 38 ns
VCC= 6.0V - 15 25 - 30 ns
Sn to nYn, nZ; see Figure14 [2]
VCC= 1.2V - 90 - - - ns
VCC= 2.0V - 32 59 - 70 ns
VCC= 2.7V - 24 44 - 52 ns
VCC= 3.0Vto 3.6V;CL =15pF[3] -16 - - - ns
VCC= 3.0 V to 3.6 V [3] - 19 36 - 42 ns
VCC= 4.5V - 17 31 - 36 ns
VCC= 6.0V - 14 24 - 28 ns
CPD power dissipation
capacitance=50 pF; fi = 1 MHz;= GNDto VCC
[4] -36 - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 15.
NXP Semiconductors 74L V4053
Triple single-pole double-throw analog switch
10.1 Waveforms
Table 9. Measurement points
< 2.7 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC
2.7 V to 3.6V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
> 3.6 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC
