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74LV259DPHIN/a4avai8-bit addressable latch
74LV259PWPHILIPSN/a10avai8-bit addressable latch


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74LV259D-74LV259PW
8-bit addressable latch
Product specification
Supersedes data of 1997 Jun 06
IC24 Data Handbook
1998 May 20
Philips Semiconductors Product specification
74LV2598-bit addressable latch
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder Output capability: standard ICC category: MSI
DESCRIPTION

The 74LV259 is a low-voltage CMOS device and is pin and function
compatible with 74HC/HCT259.
The 74LV259 is a high-speed 8-bit addressable latch designed for
general purpose storage applications in digital systems. The
74LV259 is a multifunction device capable of storing single-line data
in eight addressable latches, and also 3-to-8 decoder and
demultiplexer, with active HIGH outputs (Q0 to Q7), functions are
available. The 74LV259 also incorporate an active LOW common
reset (MR) for resetting all latches, as well as an active LOW enable
input (LE). The 74LV259 has four modes of operation as shown in
the mode select table. In the addressable latch mode, data on the
data line (D) is written into the addressed latch. The addressed latch
will follow the data input with all non-addressed latches remaining in
their previous states. In the memory mode, all latches remain in their
previous states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the addressed output
follows the state of the D input with all other outputs in the LOW
state. In the reset mode all outputs are LOW and unaffected by the
address (A0 to A2) and date (D) input. When operating the 74LV259
as an addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this should only
be done while in the memory mode. The mode select table
summarizes the operations of the 74LV259.
QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
NOTE:
CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD × VCC 2 × fi  (CL × VCC 2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
 (CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
Philips Semiconductors Product specification
74LV2598-bit addressable latch
PIN CONFIGURATION
PIN DESCRIPTION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
MODE SELECT TABLE
Philips Semiconductors Product specification
74LV2598-bit addressable latch
FUNCTION TABLE
NOTES:
= HIGH voltage level= LOW voltage level= don’t care= HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition= lower case letters indicate the state of the referenced output established during the last cycle established during the last cycle in which
it was addressed or cleared
RECOMMENDED OPERATING CONDITIONS
NOTE:
The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
Philips Semiconductors Product specification
74LV2598-bit addressable latch
ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
NOTES:
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Philips Semiconductors Product specification
74LV2598-bit addressable latch
DC ELECTRICAL CHARACTERISTICS (Continued)

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
NOTE:
All typical values are measured at Tamb = 25°C.
AC CHARACTERISTICS

GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
Philips Semiconductors Product specification
74LV2598-bit addressable latch
AC CHARACTERISTICS (Continued)

GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
NOTES:
Unless otherwise stated, all typical values are measured at Tamb = 25°C Typical values are measured at VCC = 3.3 V.
AC WAVEFORMS

VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6V;
VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
Figure 1. Enable input (LE) to output (Qn) propagation delays
and the enable input pulse width.
Figure 2. Data input (D) to output (Qn) propagation delays.
Figure 3. Address inputs (An) to output (Qn)
propagation delays.
Figure 4. Conditional reset input (MR) to output (Qn)
propagation delays.
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