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74LV164D-74LV164PW
8-bit serial-in/parallel-out shift register
Product specification
Supersedes data of 1997 Mar 28
IC24 Data Handbook
1998 May 07
Philips Semiconductors Product specification
74LV1648-bit serial-in/parallel-out shift register
FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C Gated serial data inputs Asynchronous master reset Output capability: standard ICC category: MSI
DESCRIPTIONThe 74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (Dsa or Dsb); either input can be
used as an active HIGH enable for data entry through the other
input. Both inputs must be connected together or an unused input
must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q0, which is the logical AND of
the two data inputs (Dsa, Dsb) that existed one set-up time prior to
the rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr =tf 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs. The condition is VI = GND to VCC
ORDERING INFORMATION
Philips Semiconductors Product specification
74LV1648-bit serial-in/parallel-out shift register
PIN CONFIGURATION
LOGIC SYMBOL
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
Philips Semiconductors Product specification
74LV1648-bit serial-in/parallel-out shift register
FUNCTIONAL DIAGRAM
FUNCTION TABLE = HIGH voltage level = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition = Lower case letter indicates the state of referenced input
one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
NOTES:
Philips Semiconductors Product specification
74LV1648-bit serial-in/parallel-out shift register
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTES: All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV1648-bit serial-in/parallel-out shift register
AC CHARACTERISTICSGND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
NOTE: Unless otherwise stated, all typical values are at Tamb = 25°C. Typical value measured at VCC = 3.3V. Typical value measured at VCC = 5.0V.
