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74LS377N/a20avaiOctal D-Type Flip-Flop with Common Enable and Clock
74LS377TIN/a54avaiOctal D-Type Flip-Flop with Common Enable and Clock


74LS377 ,Octal D-Type Flip-Flop with Common Enable and ClockFunctional DescriptionThe DM74LS377 consists of eight edge-triggered D flip-flops with individual D ..
74LS377 ,Octal D-Type Flip-Flop with Common Enable and ClockFeaturesThe DM74LS377 is an 8-bit register built using advanced 8-bit high speed parallel register ..
74LS377 ,Octal D-Type Flip-Flop with Common Enable and Clockfeatures the common Enablerather then common Master Reset.J SUFFIX• 8-Bit High Speed Parallel Regis ..
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74LS377
Octal D-Type Flip-Flop with Common Enable and Clock
DM74LS377 Octal D-Type Flip-Flop with Common Enable and Clock October 1988 Revised March 2000 DM74LS377 Octal D-Type Flip-Flop with Common Enable and Clock General Description Features The DM74LS377 is an 8-bit register built using advanced � 8-bit high speed parallel registers low power Schottky technology. This register consists of � Positive edge-triggered D-type flip-flops eight D-type flip-flops with a buffered common clock and a � Fully buffered common clock and enable inputs buffered common input enable. The device is packaged in the space-saving (0.3 inch row spacing) 20-pin package. Ordering Code: Order Number Package Number Package Description DM74LS377WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS377N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram V = Pin 20 CC GND = Pin 10 Pin Descriptions Truth Table Pin Names Description Inputs Output E Enable Input (Active LOW) D Q E CP n n D0–D7 Data Inputs H X X No Change CP Clock Pulse Input (Active Rising Edge) LHH Q0–Q7 Flip-Flop Outputs LLL H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial © 2000 DS009831
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