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74LS280ONN/a25avai9-bit Odd/Even Parity Generators/Checkers
74LS280N/a100avai9-bit Odd/Even Parity Generators/Checkers


74LS280 ,9-bit Odd/Even Parity Generators/CheckersThe LS280 is designed without the expander input implementation,but the corresponding function is p ..
74LS280 ,9-bit Odd/Even Parity Generators/CheckersBLOCK DIAGRAM(8)A(9)B(10)(5)∑CEVEN(11)D(12)E(13)F(6) ∑ODD(1)G(2)H(4)IDC CHARACTERISTICS OVER OPERAT ..
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74LS293 ,4-bit Binary CountersSN54/74LS290SN54/74LS293DECADE COUNTER;4-BIT BINARY COUNTERThe SN54/74LS290 and SN54/74LS293 are hi ..
74LS293 ,4-bit Binary CountersLOGIC DIAGRAMSLS290 ** ** * * * * * * ** ** ** * * * * * ** * * ** * * * * * * * * * * * * * * ..
74LS293 ,4-bit Binary CountersSN54/74LS290SN54/74LS293DECADE COUNTER;4-BIT BINARY COUNTERThe SN54/74LS290 and SN54/74LS293 are hi ..
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74LS280
LOW POWER SCHOTTKY
- The SN74LS280 is a Universal 9-Bit Parity Generator/Checker. It
features odd/even outputs to facilitate either odd or even parity. By
cascading, the word length is easily expanded.
The LS280 is designed without the expander input implementation,
but the corresponding function is provided by an input at Pin 4 and the
absence of any connection at Pin 3. This design permits the LS280 to
be substituted for the LS180 which results in improved performance.
The LS280 has buffered inputs to lower the drive requirements to one
LS unit load. Generates Either Odd or Even Parity for Nine Data Lines Typical Data-to-Output Delay of only 33 ns Cascadable for n-Bits Can Be Used To Upgrade Systems Using MSI Parity Circuits Typical Power Dissipation = 80 mW
VCC FE D C B A H NC I ∑
EVEN
GND
INPUTS INPUT
OUTPUTS
ODD
INPUTS
FUNCTION TABLE

H = HIGH Level, L = LOW Level
GUARANTEED OPERATING RANGES
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