74LS259 ,8-Bit Addressable Latchesapplicationsling the clear and enable inputs as enumerated in the func- Four distinct functional mo ..
74LS266 ,Quad 2-Input Exclusive-NOR Gate with Open-Collector OutputsGeneral DescriptionThis device contains four independent gates each of whichperforms the logic excl ..
74LS273 ,8-Bit Register with ClearSN54/74LS273OCTAL D FLIP-FLOP WITH CLEARThe SN54/ 74LS273 is a high-speed 8-Bit Register. The regis ..
74LS279 ,Quad S-R LatchGeneral DescriptionThe DM74LS279 consists of four individual and indepen-dent Set-Reset Latches wit ..
74LS279 ,Quad S-R LatchDM74LS279 Quad S-R LatchAugust 1986Revised March 2000DM74LS279Quad S-R Latch
74LS27PC , TRIPLE 3-INPUT NOR GATE
790D ,Resin-Molded, Radial-Lead Solid Tantalum CapacitorsDocument Number 42072 , contact europetantalum115Revision 26-Mar-02790DResin-Coated, Radial-LeadedV ..
7914J-1-000 , BOURNS OFFERS OVER 35 ASSORTED KITS
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7914J-1-024E , 4 mm SMD & Through-hole Sealed Key Switch
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79L06 , TO-92 Plastic-Encapsulate Transistors
74LS259
8-Bit Addressable Latches
DM74LS259 8-Bit Addressable Latches August 1986 Revised March 2000 DM74LS259 8-Bit Addressable Latches General Description Features These 8-bit addressable latches are designed for general � 8-Bit parallel-out storage register performs serial-to-par- purpose storage applications in digital systems. Specific allel conversion with storage uses include working registers, serial-holding registers, � Asynchronous parallel clear and active-high decoders or demultiplexers. They are mul- � Active high decoder tifunctional devices capable of storing single-line data in � Enable/disable input simplifies expansion eight addressable latches, and being a 1-of-8 decoder or � Direct replacement for Fairchild DM9334 demultiplexer with active-high outputs. Four distinct modes of operation are selectable by control- � Expandable for N-bit applications ling the clear and enable inputs as enumerated in the func- � Four distinct functional modes tion table. In the addressable-latch mode, data at the data- � Typical propagation delay times: in terminal is written into the addressed latch. The Enable-to-output 18 ns addressed latch will follow the data input with all unad- Data-to-output 16 ns dressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states Address-to-output 21 ns and are unaffected by the data or address inputs. To elimi- Clear-to-output 17 ns nate the possibility of entering erroneous data in the � Fan-out latches, the enable should be held HIGH (inactive) while I (sink current) 8 mA the address lines are changing. In the 1-of-8 decoding or OL demultiplexing mode, the addressed output will follow the I (source current) −0.4 mA OH level of the D input with all other outputs LOW. In the clear � Typical I 22 mA CC mode, all outputs are LOW and unaffected by the address and data inputs. Ordering Code: Order Number Package Number Package Description DM74LS259M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS259WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS259N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006418
