74LS251 ,3-STATE 1-of-8 Line Data Selector/MultiplexerFeaturesThese data selectors/multiplexers contain full on-chip 3-STATE version of DM74LS151binary ..
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74LS251
3-STATE 1-of-8 Line Data Selector/Multiplexer
DM74LS251 3-STATE 1-of-8 Line Data Selector/Multiplexer August 1986 Revised March 2000 DM74LS251 3-STATE 1-of-8 Line Data Selector/Multiplexer General Description Features These data selectors/multiplexers contain full on-chip � 3-STATE version of DM74LS151 binary decoding to select one-of-eight data sources, and � Interface directly with system bus feature a strobe-controlled 3-STATE output. The strobe � Perform parallel-to-serial conversion must be at a low logic level to enable these devices. The 3- � Permit multiplexing from N-lines to one line STATE outputs permit direct connection to a common bus. When the strobe input is HIGH, both outputs are in a high- � Complementary outputs provide true and inverted data impedance state in which both the upper and lower transis- � Maximum number of common outputs: 129 tors of each totem-pole output are OFF, and the output nei- � Typical propagation delay time (D to Y): 17 ns ther drives nor loads the bus significantly. When the strobe � Typical power dissipation: 35 mW is LOW, the outputs are activated and operate as standard TTL totem-pole outputs. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output con- trol circuitry is designed so that the average output disable time is shorter than the average output enable time. Ordering Code: Order Number Package Number Package Description DM74LS251M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS251N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs Select Strobe YW CBA S XX X H Z Z LL L L D0 D0 LL H L D1 D1 LH L L D2 D2 LH H L D3 D3 HL L L D4 D4 HL H L D5 D5 HH L L D6 D6 HHH L D7 D7 H = HIGH Logic Level L = LOW Logic Level X = Don't Care Z = High Impedance (OFF) D0, D1…D7 = The level of the respective D input © 2000 DS006415
