74LS195APC ,21 mA; universal 4-bit shift registerapplications by tying the two pins together. When thePTiinput is LOW, the '195 appears as
four com ..
74LS195APC ,21 mA; universal 4-bit shift registerapplications. It
performs serial, parallel, serial to parallel, or parallel to serial d_ata transf ..
74LS196 ,4-STAGE PRESETTABLE RIPPLE COUNTERSLOGIC DIAGRAM* * * ** * * * ** * ** * * ** * * ** * * * * * * * * ** * * * * ** * * * * * * * * ..
74LS197 ,4-STAGE PRESETTABLE RIPPLE COUNTERSLOGIC DIAGRAM* * * ** * * * ** * ** * * ** * * ** * * * * * * * * ** * * * * ** * * * * * * * * ..
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74LS20 ,Dual 4-Input NAND GateGeneral DescriptionThis device contains two independent gates each of whichperforms the logic NAND ..
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78P2344JAT-IGT , 4-port E3/DS3/STS-1 LIU with Jitter Attenuator
54195DM-74195DC-74LS195APC
63 mA; universal 4-bit shift register
I XNATI0NAL SEMICONb {LOGIC} DEE I)
. {.14. A.
n LSULLEB 0053156 i, t
93L00 and 93H00.
1 95 719/0er
CONNECTION DIAGRAM
PINOUT A
54LS/74LS195A tart, V :1
UNIVERSAL 4-BIT SHIFT REGISTER J 2 isiloo
i 3 Elm
PaE Etta
PIE EC:
Pe 6 Ea:
DESCRIPTION-The '195 is a high speed 4-bit shift register offering typical
shift frequencies of 50 MHz. It is useful for a wide variety of register and PaE Ecp
counting applications. The '195 is pin and functionally identical to the 9300, GNDE Ere
I TYPICAL SHIFT RIGHT FREQUENCY OF 50 MHai'LS195A)
q ASYNCHRONOUS MASTER RESET
. J, R INPUTS TO FIRST STAGE
. FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS
ORDERING CODE.' See Section 9
pm COMMERCIAL GRADE MILITARY GRADE PKG
PKGS OUT Ttei-i/ffl/tsit/i':', (',eeCiistr?ll/'i1th, TYPE
3?}; A 74195PC, 74LS195APC 9B
3:333“ A 7419500,74LS195ADC 54195DM, 54LS195ADM 6B
"2" A 74195FC, 74LS195AFC 54195FM, 54LS195AFM 4L
LOGIC SYMBOL
to-ict' th O-lt
MR000| 02 th
1 15141312
Vcc = Pin 16
Gnd = Pin 8
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
54/74 (U.L.) 54/74LS (U.L.)
PIN NAMES DESCRIPTION HIGH/LOW HIGH/LOW
PTi Parallel Enable Input (Active LOW) 1.0/1.0 0.5/0.25
Po- P3 Parallel Data Inputs 1.0/1.0 0.5/0.25
J First Stage J Input (Active HIGH) 1.0/1.0 0.5/0.25
R _ First Stage K Input (Active LOW) 1.0/1.0 0.5/0.25
GP Clock Pulse Input (Active Rising Edge) 1.0/1.0 0.5/0.25
"iTi'i _ Asynchronous Master Reset Input 1.0/1.0 0.5/0.25
(Active LOW)
00 - 03 Parallel Outputs 20/10 10/5.0
53 Complementary Last Stage Output 20/10 10/5.0
(Active LOW) (2.5)
4-296 THe- toe
' r1414:
i..' Nh'T)/1hl- SEH-ICOND {LOGIC} DEE I) DESDLLBB DDEB‘BL ll
§ffg-oy-or '
FUNCTIONAL DESCRIPTION --The Logic Diagram and Truth Table indicate the functional characteristics of
the '195 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It
performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The '195 has two primary modes of operation, shift right(Qo-) 01) and parallel load, which are controlled bythe
state of the Parallel Enable (PE) Input. When thePEinput is HIGH, serial data entersthe first tlip-tlop 00 via the J
and R inputs and is shifted one bit in the direction t20--'th-s02-9 l following each LOW-to-HIGH clock
transition. The JR' inputs provide the flexibility of the JK type input for spec_ia| applications, and the simple D
type input for general applications by tying the two pins together. When the PE input is LOW, the '195 appears as
tour common clocked D flip-flops. The data on the parallel inputs Po, P1, P2, Pa istransterred to the respective
Co, O1. 02. l outputs following the LOW-to-HIGH clock transition. Shift left operation (03-H22) can be
achieved by tying the On outputs to-the Pn - 1 inputs and holding the PE input LOW.
All serial and parallel data transfers aresynchronous, occuring attereach LOW-to-HIGH clock transition. Since
the '195 utilizes edge-triggering, there is no restriction on the activity of the J, R, Pn and P-E inputs tor logic
operation - except for the setup and release time requirements. A LOW on the asynchronous Master Reset
am) input sets all Q outputs LOW, independent of any other input condition.
MODE SELECT TABLE
OPERATING MODES - “'NPUTE OUTPUTS -
MR PE J K Pn Go th th 03 th
Asynchronous Reset L X X X X L L L L H
Shift, Set First Stage H h h h X H qo Q1 q2 62
Shift, Reset First Stage H h l I X L qo q1 q2 t-qa
Shift, Toggle First Stage H h h I X tis qo q1 q2 Fqa
Shift, Retain Flrst Stage H h l h X qo qo q1 q2 t-ie
Parallel Load H I x X Pn po p1 p2 pa 53
H = HIGH Voltage Level L = LOW Voltage Level x = Immaterial
I = LOW voltage level one setup time prior to the LOW to HIGH clock transition.
h = HIGH voltage level one setup time prior to the LOW to HIGH clock transition.
pn (qn) = Lower case letters indicate the state of the referenced input tor output) one setup time prior to
the LOW to HIGH clock transition.
LOGIC DIAGRAM
" J g " Pt Pp Pa
t _ i)
l I, I O
ft 0060 R Ca R Co R 'ma,
--0 cr -o CP -
Hr-- tr no Hr-: s o. - s a; -, Her- 5 o: -l
Go lh th 0353
1329 o-ot, 4-297 f7/535",2/g
'11 1A
, NATIONAL SEMIC'OM). 'i‘Lbéi-C} -DEE-l.). 1rasuouieie nnbjaaé'u‘n
195 17"76-09-05 '
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE1unless otherwise specified)
SYMBOL PARAMETER M/74 54/74LS UNITS CONDITIONS
Min Max Min Max
T Vc.p. = M&PE= Gnd
Icc Power Supply Current 63 21 mA J, K, Pn, R = .5 V
GP = =
AC CHARACTERISTICS: Vcc = +5.0 V. TA = +25°C (See Section 3 for waveforms and load configurations)
54/74 54/74LS
SYMBOL PARAMETER CL = 15 pF th. Tir. 15 pF UNITS CONDITIONS
RL = 400 n
Min Max Min Max
fmax Maximum Clock Frequency 30 30 MHz Figs. 3-1,3-8
tPLH Propagation Delay 22 21 s
tPHL GP to On " 26 24 n
tPHL Propagation rosgay,M-R to On 30 26 ns Figs. 3-1, 3-16
AC OPERATING REQUIREMENTS: Vcc = +5.0 V, TA = +25°C
SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS
Min Max Min Max
15(H) Selyp Time HIGH or LOW 20 15 ns
15(L) J, K or Pn to GP 20 15
tn (H) Hold Time HIGH or LOW 0 0 ns
th (L) J, K or Pn to CP 0 0 Fig. 3-6
ts (H) Setup Time HIGH or LOW 25 25
tstL) E to GP 25 25 ns
th1H) Egld Time HIGH or LOW -10 0
th (L) PE to CP -10 o ns
tw (H) GP Pulse Width HIGH 16 16 ns Fig. 3-8
tw (L) MR Pulse widthelw 12 12 ns Fig, 3-16
tree Recovery Time, MR to GP 25 20 ns
1330 0-09 4-298 57/791}?
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
74195DM - product/74195dm?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nu||-wwe
74195DC - product/74195dc?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
74195FC - product/74195fc?HQS=T|—null-null-dscatalog—df—pf—nuII-wwe
54LS195AFM - product/54Is195afm?HQS=T|-nu|I-null-dscatalog-df—pf-nuII-wwe
54LS195ADM - product/54Is195adm?HQS=TI-nu|I-nu|I-dscataIog-df-pf-null-wwe
74195PC - product/74195pc?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nuII-wwe
74LS195ADC - product/74Is195adc?HQS=Tl-nuIl-nu|I-dscataIog-df-pf-null-wwe
74LS195AFC - product/74Is195afc?HQS=T|—nuII-nu|I-dscatalog-df-pf-nuII-wwe
74LS195APC - product/74Is195apc?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
54195FM - product/54195fm?HQS=T|-nulI-nuIl-dscatalog-df-pf-nulI-wwe
54195DM - product/54195dm?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nuIl-wwe
