74LS193 ,Synchronous Up/Down 4-bit Binary Counters(dual clock lines)General Descriptioninputs are buffered to lower the drive requirements of clockThe DM74LS193 circui ..
74LS194A ,LOW POWER SCHOTTKY
74LS195 ,4-bit Parallel-Access Shift RegistersLOGIC DIAGRAM** * * * * * * ** * * ** * * * * * * * * * * * * * * * * ** ** ** * * * * * * ** * ..
74LS195APC ,21 mA; universal 4-bit shift registerapplications by tying the two pins together. When thePTiinput is LOW, the '195 appears as
four com ..
74LS195APC ,21 mA; universal 4-bit shift registerapplications. It
performs serial, parallel, serial to parallel, or parallel to serial d_ata transf ..
74LS196 ,4-STAGE PRESETTABLE RIPPLE COUNTERSLOGIC DIAGRAM* * * ** * * * ** * ** * * ** * * ** * * * * * * * * ** * * * * ** * * * * * * * * ..
78M18 , LINEAR INTEGRATED CIRCUITS 3-TERMINAL VOLATGE REGULATORS
78M18 , LINEAR INTEGRATED CIRCUITS 3-TERMINAL VOLATGE REGULATORS
78M6612-IGT/F ,Single-Phase, Dual-Outlet Power and Energy Measurement IC
78M6612-IMR/F/PD ,Single-Phase, Dual-Outlet Power and Energy Measurement IC
78P2241-IGT , Transceiver
78P2344JAT-IGT , 4-port E3/DS3/STS-1 LIU with Jitter Attenuator
74LS193
Synchronous 4-Bit Binary Counter with Dual Clock
DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock of the count and load inputs. The clear, count, and load General Description inputs are buffered to lower the drive requirements of clock The DM74LS193 circuit is a synchronous up/down 4-bit drivers, etc., required for long words. binary counter. Synchronous operation is provided by hav- These counters were designed to be cascaded without the ing all flip-flops clocked simultaneously, so that the outputs need for external circuitry. Both borrow and carry outputs change together when so instructed by the steering logic. are available to cascade both the up and down counting This mode of operation eliminates the output counting functions. The borrow output produces a pulse equal in spikes normally associated with asynchronous (ripple- width to the count down input when the counter underflows. clock) counters. Similarly, the carry output produces a pulse equal in width The outputs of the four master-slave flip-flops are triggered to the count down input when an overflow condition exists. by a LOW-to-HIGH level transition of either count (clock) The counters can then be easily cascaded by feeding the input. The direction of counting is determined by which borrow and carry outputs to the count down and count up count input is pulsed while the other count input is held inputs respectively of the succeeding counter. HIGH. The counter is fully programmable; that is, each output may Features be preset to either level by entering the desired data at the � Fully independent clear input inputs while the load input is LOW. The output will change independently of the count pulses. This feature allows the � Synchronous operation counters to be used as modulo-N dividers by simply modi- � Cascading circuitry provided internally fying the count length with the preset inputs. � Individual preset each flip-flop A clear input has been provided which, when taken to a high level, forces all outputs to the low level; independent Ordering Code: Order Number Package Number Package Description DM74LS193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Connection Diagram © 2000 DS006406
