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74LS175-SN54LS175J-SN74LS175N Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
74LS175MITSN/a211avaiLOW POWER SCHOTTKY
SN54LS175JTMN/a20avaiQUAD D FLIP-FLOP
SN74LS175NMOTN/a1895avaiQUAD D FLIP-FLOP


SN74LS175N ,QUAD D FLIP-FLOPSN54/74LS175QUAD D FLIP-FLOPThe LSTTL /MSI SN54 /74LS175 is a high speed Quad D Flip-Flop. Thedevic ..
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74LS175-SN54LS175J-SN74LS175N
LOW POWER SCHOTTKY
QUAD D FLIP-FLOP
The LSTTL/MSI SN54/74LS175 is a high speed Quad D Flip-Flop. The
device is useful for general flip-flop requirements where clock and clear inputs
are common. The information on the D inputs is stored during the LOW to
HIGH clock transition. Both true and complemented outputs of each flip-flop
are provided. A Master Reset input resets all flip-flops, independent of the
Clock or D inputs, when LOW.
The LS175 is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families. Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES LOADING (Note a)

D0–D3
Q0–Q3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs (Note b)
Complemented Outputs (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
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