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74LS126ATIN/a22900avaiQuad TRI-STATE Buffer


74LS126A ,Quad TRI-STATE BufferDM74LS126AQuadTRI-STATEBufferSeptember1991DM74LS126AQuadTRI-STATE BufferÉGeneralDescriptionThis dev ..
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74LS126A
Quad TRI-STATE Buffer
TL/F/6388
DM74LS126A
Quad
TRI-STATE
Buffer
September 1991
DM74LS126A Quad TRI-STATEÉ Buffer
General Description
This device contains four independent gates eachof which
performsa non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled,the outputs exhibit
thelow impedance characteristicsofa standardLS output
with additional drive capabilityto permitthe drivingofbus
lines without external resistors. When disabled, boththe
output transistorsare turnedoff presentinga high-imped-
ance stateto thebus line. Thusthe outputwillact neitheras significant loadnorasa driver.To minimizethe possibility
thattwo outputswill attemptto takea commonbusto oppo-
site logic levels,the disable timeis shorter thanthe enable
timeofthe outputs.
Connection Diagram
Dual-In-Line Package
TL/F/6388–1
Order Number DM74LS126AMor DM74LS126AN
SeeNSPackage Number M14Aor N14A
Function TableeA
Inputs Output Y L H L Hi-ZeHigh Logic LeveleLow Logic Levele EitherLow orHighLogicLevel
Hi-Ze TRI-STATE (Outputsare disabled)
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
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