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74LS126N/AN/a50avaiQuad 3-STATE Buffer
74LS126N/a20avaiQuad 3-STATE Buffer


74LS126 ,Quad 3-STATE BufferGeneral DescriptionThis device contains four independent gates each of whichperforms a non-invertin ..
74LS126 ,Quad 3-STATE BufferDM74LS126A Quad 3-STATE BufferAugust 1986Revised March 2000DM74LS126AQuad 3-STATE Buffer
74LS126A ,Quad TRI-STATE BufferDM74LS126AQuadTRI-STATEBufferSeptember1991DM74LS126AQuadTRI-STATE BufferÉGeneralDescriptionThis dev ..
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74LS136 ,Quad 2-Input Exclusive-OR Gate with Open-Collector OutputsDM74LS136 Quad 2-Input Exclusive-OR Gate with Open-Collector OutputsOctober 1988Revised March 2000D ..
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78L05A , 3-Terminal Regulators
78L05A , 3-Terminal Regulators
78L05A , 3-Terminal Regulators
78L05A , 3-Terminal Regulators


74LS126
Quad 3-STATE Buffer
DM74LS126A Quad 3-STATE Buffer August 1986 Revised March 2000 DM74LS126A Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned OFF presenting a high-imped- ance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possi- bility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. Ordering Code: Order Number Package Number Package Description DM74LS126AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS126AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = A Inputs Output AC Y LH L HH H X L Hi-Z H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level Hi-Z = 3-STATE (Outputs are disabled) © 2000 DS006388
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