SN54LS112J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOPSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
SN54LS112J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOPfeatures individual J, K, clock, andasynchronous set and clear inputs to each flip-flop. When the c ..
SN54LS113J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54LS114J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54LS125AJ ,Quad 3-state bufferSN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126AThe SN54125, SN54 ..
SN54LS125J ,QUAD 3-STATE BUFFERS
SN74GTL1655 ,16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live InsertionSCBS696I–JULY 1997–REVISED APRIL 2005DESCRIPTION/ORDERING INFORMATION (CONTINUED)This device is par ..
SN74GTL1655DGGR ,16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live InsertionSCBS696I–JULY 1997–REVISED APRIL 2005FUNCTION TABLESABC(1)FUNCTIONINPUTSOUTPUTMODEBOEAB LEAB CLK AH ..
SN74GTL1655DGGRG4 , 16-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION
SN74GTL16612ADGGR , 18-BIT LVTTL-TO-GTL/GTLPLUS UNIVERSAL BUS TRANSCEIVERS
SN74GTL16612ADGGR , 18-BIT LVTTL-TO-GTL/GTLPLUS UNIVERSAL BUS TRANSCEIVERS
SN74GTL16612DGGR ,18-Bit LVTTL-to-GTL/GTL+ Universal Bus TransceiversFEATURESSN54GTL16612. . . WD PACKAGE• Members of Texas Instruments Widebus™SN74GTL16612. . . DGG OR ..
74LS112-SN54LS112J-SN74LS112N
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)- ---- ----
MODE SELECT — TRUTH TABLE Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
