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Home ›  7720 > 74LCX74BQX-74LCX74M-74LCX74MTC-74LCX74MTCX-74LCX74MX-74LCX74SJX,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX74BQX-74LCX74M-74LCX74MTC-74LCX74MTCX-74LCX74MX Fast Delivery,Good Price
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74LCX74BQXFAIN/a3avaiLow Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX74MFAIRCHILDN/a150avaiCMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUT
74LCX74MTCFAIRCHILDN/a4518avaiLow Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX74MTCXFAIRCHILD 仙童N/a2500avaiLow Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX74MXFAIRCHILN/a4980avaiLow Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX74SJXFAIRCHILD N/a1802avaiLow Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX74SJXFAIN/a1380avaiLow Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs


74LCX74MX ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant InputsFeaturesThe LCX74 is a dual D-type flip-flop with Asynchronous

74LCX74BQX-74LCX74M-74LCX74MTC-74LCX74MTCX-74LCX74MX-74LCX74SJX
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs March 1995 Revised February 2005 74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX74 is a dual D-type flip-flop with Asynchronous5V tolerant inputs Clear and Set inputs and complementary (Q, Q) outputs.2.3V–3.6V V specifications provided CC Information at the input is transferred to the outputs on the 7.0 ns t max (V 3.3V), 10 PA I max PD CC CC positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input isPower down high impedance inputs and outputs locked out and information present will not be transferred tor24 mA output drive (V 3.0V) CC the outputs until the next rising edge of the Clock Pulse Implements patented noise/EMI reduction circuitry input. Latch-up performance exceeds JEDEC 78 conditions Asynchronous Inputs: ESD performance: LOW input to S (Set) sets Q to HIGH level D Human body model ! 2000V LOW input to C (Clear) sets Q to LOW level D Machine model ! 200V Clear and Set are independent of clock Leadless Pb-Free DQFN package Simultaneous LOW on C and S makes both Q and D D Q HIGH Ordering Code: Package Order Number Package Description Number 74LCX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LCX74MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 2) 74LCX74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX74BQX MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC (Note 1) MO-241, 2.5 x 3.0mm 74LCX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LCX74MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 2) Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: DQFN package available in Tape and Reel only. Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 DS012414
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