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74LCX573MTRSTN/a19000avaiOCTAL D-TYPE NON INVERTING WITH 5V TOLERANT INPUT AND OUTPUT
74LCX573TTRSTN/a3740avaiOCTAL D-TYPE NON INVERTING WITH 5V TOLERANT INPUT AND OUTPUT


74LCX573MTR ,OCTAL D-TYPE NON INVERTING WITH 5V TOLERANT INPUT AND OUTPUT74LCX573OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)WITH 5V TOLERANT INPUTS AND OUTPUTS ■ 5V TOLERAN ..
74LCX573TTR ,OCTAL D-TYPE NON INVERTING WITH 5V TOLERANT INPUT AND OUTPUTAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX573WMX ,Low Voltage Octal Latch with 5V Tolerant Input and Outputs74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and OutputsMarch 1995Revised March 200174L ..
74LCX573WMX ,Low Voltage Octal Latch with 5V Tolerant Input and OutputsFeaturesThe LCX573 is a high-speed octal latch with buffered com-

74LCX573MTR-74LCX573TTR
OCTAL D-TYPE NON INVERTING WITH 5V TOLERANT INPUT AND OUTPUT
1/10September 2001 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED :PD = 8.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION

The 74LCX573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while (OE) is in high level, the
outputs will be in a high impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX573

OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LCX573
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION TRUTH TABLE

X : Don’t Care
Z : High Impedance
* : Q Outputs are latched at the time when the LE input is taken
LOW.
LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays
74LCX573
3/10
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
RECOMMENDED OPERATING CONDITIONS

1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
74LCX573
4/10
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS

1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX573
5/10
AC ELECTRICAL CHARACTERISTICS

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per latch)
74LCX573
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TEST CIRCUIT

CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE PULSE WIDTH, Dn TO LE SETUP AND
HOLD TIMES (f=1MHz; 50% duty cycle)
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