74LCX373 ,D-TYPE LATCH NON INVERTING WITH 5V TOLERANT INPUT AND OUTPUTAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX373BQX ,Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputsapplications with capability ofCCinterfacing to a 5V signal environment.
74LCX373
D-TYPE LATCH NON INVERTING WITH 5V TOLERANT INPUT AND OUTPUT
1/13September 2004 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED:
tPD = 8.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched precisely
at the logic level of D input data. While the (OE)
input is low, the 8 outputs will be in a normal logic
state (high or low logic level) and while (OE) is in
high level, the outputs will be in a high impedance
state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX373OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 5
74LCX3732/13
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description Table 3: Truth Table X : Don’t Care
Z : High Impedance
* : Q Outputs are latched at the time when the LE input is taken
LOW.
Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays
74LCX3733/13
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
74LCX3734/13
Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX3735/13
Table 8: AC Electrical Characteristics 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per latch)
74LCX3736/13
Figure 4: Test Circuit CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 5: Waveform - LE To Qn Propagation Delays, LE Minimum Pulse Width, Dn To LE Setup
And Hold Times (f=1MHz; 50% duty cycle)
74LCX3737/13
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)
