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74LCX16245TTRSTN/a1025avaiLOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
74LCX16245TTRSTMIN/a2000avaiLOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
74LCX16245TTRSTMN/a4000avaiLOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS


74LCX16245TTR ,LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX16245TTR ,LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTSapplications; it can beinterfaced to 5V signal environment for both inputsand outputs.This IC is in ..
74LCX16373 ,Low-Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and OutputsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX16373G ,Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputsapplications with capability of interfacing to a 5V signalCCenvironment.

74LCX16245TTR
LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
1/10February 2003 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED:
tPD= 4.5ns (MAX.)at VCC =3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL= 24mA (MIN)at VCC =3V PCI BUS LEVELS GUARANTEED AT24 mA BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR)= 2.0Vto 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH SERIES 16245 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM> 2000V (MIL STD 883 method 3015);> 200V
DESCRIPTION

The 74LCX16245isa low voltage CMOS 16 BIT
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiringC2 MOS technology.Itis ideal for low power
and high speed 3.3V applications;it can be
interfacedto5V signal environmentfor both inputs
and outputs.
This ICis intended for two-way asynchronous
communication between data buses; the direction data transmissionis determinedby DIR input.
The two enable inputs nG can beusedtodisable
the deviceso that the buses are effectively isolat-
ed. has same speed performanceat 3.3V than 5V
AC/ACT family, combined witha lower power con-
sumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
All floating bus terminals during HighZ State must held HIGHor LOW.
74LCX16245

LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER
WITH 5V TOLERANT INPUTS AND OUTPUT (3-STATE)
ORDER CODES
PIN CONNECTION
74LCX16245
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
: Don‘t Care: High Impedance
IEC LOGIC SYMBOLS
74LCX16245
3/10
ABSOLUTE MAXIMUM RATINGS

AbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not impliedIO absolute maximum rating mustbe observedVO
RECOMMENDED OPERATING CONDITIONS Truth Table guaranteed: 1.5Vto 3.6VVIN from 0.8Vto2Vat VCC =3.0V
74LCX16245
4/10 SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS
Numberof outputs definedas"n". Measured with "n-1" outputs switching from HIGHto LOWor LOWto HIGH. The remaining outputis
measuredinthe LOW state.
74LCX16245
5/10 ELECTRICAL CHARACTERISTICS Skewis defined astheabsolute value ofthedifference betweenthe actual propagation delayfor anytwo outputsofthe samedevice switch-
inginthe same direction, either HIGHor LOW (tOSLH =|tPLHm -tPLHn|, tOSHL =|tPHLm -tPHLn|) Parameter guaranteedby design
CAPACITIVE CHARACTERISTICS
CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load. (Referto Test Circuit). Average operating currentcanbe obtainedbythe following equation. ICC(opr) =CPD xVCC xfIN +ICC/16 (per
circuit)
74LCX16245
6/10
TEST CIRCUIT
=50pFor equivalent (includesjig and probe capacitance) =R1= 500Ω or equivalent =ZOUTof pulse generator (typically 50Ω)
WAVEFORM1: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
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