74LCX16240MTDX ,Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputsapplications with capacity of interfacing to a 5V signalCC
74LCX16240MEAX-74LCX16240MTD-74LCX16240MTDX
Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs
74LCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs and Outputs February 1994 Revised November 2001 74LCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs and Outputs General Description Features The LCX16240 contains sixteen inverting buffers with5V tolerant inputs and outputs 3-STATE outputs designed to be employed as a memory2.3V to 3.6V V specifications provided CC and address driver, clock driver, or bus-oriented transmit- 4.5 ns t max (V = 3.3V), 20 μA I max PD CC CC ter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shortedPower down high impedance inputs and outputs together for full 16-bit operation.Supports live insertion/withdrawal (Note 1) The LCX16240 is designed for low voltage (2.5V or 3.3V)±24 mA output drive (V = 3.0V) CC V applications with capacity of interfacing to a 5V signal CC Implements patented noise/EMI reduction circuitry environment. Latch-up performance exceeds 500 mA The LCX16240 is fabricated with an advanced CMOS tech- ESD performance: nology to achieve high speed operation while maintaining CMOS low power dissipation. Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to V through a pull-up resistor: the minimum value or the CC resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX16240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LCX16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Inputs (Active LOW) n I –I Inputs 0 15 O –O Outputs 0 15 GTO is a trademark of . © 2001 DS011999
