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74LCX14FAIRCHILDN/a1100avaiLow Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs


74LCX14 ,Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger InputsFeaturesThe LCX14 contains six inverter gates each with a Schmitt

74LCX14
Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs March 1995 Revised January 2001 74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs General Description Features The LCX14 contains six inverter gates each with a Schmitt5V tolerant inputs trigger input. They are capable of transforming slowly2.3V–3.6V V specifications provided CC changing input signals into sharply defined, jitter-free out- 6.5 ns t max (V = 3.3V), 10 μA I max PD CC CC put signals. In addition, they have a greater noise margin than conventional inverters.Power down high impedance inputs and outputs The LCX14 has hysteresis between the positive-going and±24 mA output drive (V = 3.0V) CC negative-going input thresholds (typically 1.0V) which is Implements patented noise/EMI reduction circuitry determined internally by transistor ratios and is essentially Latch-up performance exceeds 500 mA insensitive to temperature and supply voltage variations. ESD performance: The inputs tolerate voltages up to 7V allowing the interface Machine model > 2000V of 5V, 3V and 2.5V systems. Human model > 200V The 74LCX14 is fabricated with advanced CMOS technol- ogy to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Code: Order Number Package Number Package Description 74LCX14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LCX14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Truth Table Pin Descriptions Input Output Pin Names Description AO I Inputs L H n O Outputs H L n © 2001 DS012412
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