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74LCX07N/a33avaiLOW VOLTAGE HEX BUFFER (OPEN DRAIN) WITH 5V TOLERANT INPUTS


74LCX07 ,LOW VOLTAGE HEX BUFFER (OPEN DRAIN) WITH 5V TOLERANT INPUTSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX07M ,LOW VOLTAGE HEX BUFFER (OPEN DRAIN) WITH 5V TOLERANT INPUTSFeaturesThe LCX07 contains six buffers. The inputs tolerate volt-

74LCX07
LOW VOLTAGE HEX BUFFER (OPEN DRAIN) WITH 5V TOLERANT INPUTS
1/11September 2004 5V TOLERANT INPUTS HIGH SPEED:
tPD = 5.2ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 07 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION

The 74LCX07 is a low voltage CMOS OPEN
DRAIN HEX BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and high
speed 3.3V applications. It can be interfaced to 5V
signal environment for inputs.
The internal circuit is composed of 2 stages
including buffer output, which provides high noise
immunity and stable output.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX07

LOW VOLTAGE CMOS HEX BUFFER (OPEN DRAIN)
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes

Rev. 4
74LCX07
2/11
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description Table 3: Truth Table

Z : High Impedance
Table 4: Absolute Maximum Ratings

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
74LCX07
3/11
Table 5: Recommended Operating Conditions

1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics

1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX07
4/11
Table 8: AC Electrical Characteristics

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/6 (per gate)
Figure 3: Test Circuit

CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LCX07
5/11
Figure 4: Waveform - Propagation Delay (f=1MHz; 50% duty cycle)

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