74HC93DB ,74HC/HCT93; 4-bit binary ripple counterFEATURES divide-by-two section and a the device may be operated in variousdivide-by-eight section. ..
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74HCT00DB ,Quad 2-input NAND gate
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74HC93D-74HC93DB-74HCT93D
74HC/HCT93; 4-bit binary ripple counter
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
FEATURES Various counting modes Asynchronous master reset Output capability: standard ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT93 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT93 are 4-bit binary
ripple counters. The devices consist
of four master-slave flip-flops
internally connected to provide a
divide-by-two section and a
divide-by-eight section. Each section
has a separate clock input (CP0 and
CP1) to initiate state changes of the
counter on the HIGH-to-LOW clock
transition. State changes of the Qn
outputs do not occur simultaneously
because of internal ripple delays.
Therefore, decoded output signals
are subject to decoding spikes and
should not be used for clocks or
strobes.
A gated AND asynchronous master
reset (MR1 and MR2) is provided
which overrides both clocks and
resets (clears) all flip-flops.
Since the output from the
divide-by-two section is not internally
connected to the succeeding stages,
the device may be operated in various
counting modes. In a 4-bit ripple
counter the output Q0 must be
connected externally to input CP1.
The input count pulses are applied to
clock input CP0. Simultaneous
frequency divisions of 2, 4, 8 and 16
are performed at the Q0, Q1, Q2 and
Q3 outputs as shown in the function
table. As a 3-bit ripple counter the
input count pulses are applied to input
CP1.
Simultaneous frequency divisions of
2, 4 and 8 are available at the Q1, Q2
and Q3 outputs. Independent use of
the first flip-flop is available if the reset
function coincides with reset of the
3-bit ripple-through counter.
QUICK REFERENCE DATAGND= 0 V; Tamb =25 °C; tr =tf= 6 ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi +∑ (CL× VCC2× fo) where:= input frequency in MHz; fo= output frequency in MHz (CL× VCC2×fo)= sum of outputs= output load capacitance in pF; VCC= supply voltage in V For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
PIN DESCRIPTION
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
FUNCTION TABLE
Notes Output Q0 connected to CP1.= HIGH voltage level= LOW voltage level
MODE SELECTION
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HCGND= 0 V; tr =tf= 6 ns; CL= 50 pF
Philips Semiconductors Product specification
4-bit binary ripple counter 74HC/HCT93
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCTGND= 0 V; tr =tf= 6 ns; CL= 50 pF
