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74HC373DBPHILIPSN/a1182avai74HC/HCT373; Octal D-type transparent latch; 3-state
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74HC373DB-74HC373PW-74HCT373D-74HCT373DB -74HCT373N-74HCT373PW
74HC/HCT373; Octal D-type transparent latch; 3-state

Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT373
FEATURES
3-state non-inverting outputs for bus oriented
applications Common 3-state output enable input Functionally identical to the “563”, “573” and “533” Output capability: bus driver ICC category: MSI
GENERAL DESCRIPTION

The 74HC/HCT373 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT373 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
latches.
The “373” consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the Dn
inputs enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The “373” is functionally identical to the “533”, “563” and
“573”, but the “563” and “533” have inverted outputs and
the “563” and “573” have a different pin arrangement.
QUICK REFERENCE DATA

GND=0 V; Tamb =25 °C; tr =tf= 6 ns
Notes
CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi +∑ (CL× VCC2× fo) where:= input frequency in MHz= output frequency in MHz (CL× VCC2×fo)= sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC. For HCT the condition is VI= GND to VCC− 1.5V
ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT373
PIN DESCRIPTION
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT373
FUNCTION TABLE
Notes
H= HIGH voltage level= HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition= LOW voltage level= LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition= don’t care= high impedance OFF-state
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT373
DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC

GND=0 V; tr =tf=6 ns; CL =50pF
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT373
DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types

The value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT

GND=0 V; tr =tf=6 ns; CL =50pF
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