74HC10D ,74HC/HCT10; Triple 3-input NAND gatePin configuration. Fig.2 Logic symbol.FUNCTION TABLEINPUTS OUTPUTnA nB nC nYLLL HLL H HLHL HLH H H ..
74HC10DB ,Triple 3-input NAND gateGENERAL DESCRIPTIONThe 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with l ..
74HC10E , TRIPLE 3-INPUT NAND GATE
74HC10N ,Triple 3-input NAND gatePin configuration. Fig.2 Logic symbol.FUNCTION TABLEINPUTS OUTPUTnA nB nC nYLLL HLL H HLHL HLH H H ..
74HC112D ,dual JK flip-flop with set and reset; negative-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC112N ,dual JK flip-flop with set and reset; negative-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74LS75 ,Quad LatchSN54/74LS754-BIT D LATCHSN54/74LS77The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem- ..
74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74LS90 ,Decade and Binary CountersLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS921 14CP CP1 02 13NCNCJ Q J Q J Q J Q143 12NC Q0CPC ..
74LS90 ,Decade and Binary Counters
74LS90 ,Decade and Binary CountersSN54/74LS90SN54/74LS92DECADE COUNTER;SN54/74LS93DIVIDE-BY-TWELVE COUNTER;4-BIT BINARY COUNTERDECADE ..
74HC10D-74HC10DB-74HCT10D
Triple 3-input NAND gate
Philips Semiconductors Product specification
Triple 3-input NAND gate 74HC/HCT10
FEATURES Output capability: standard ICC category: SSI
GENERAL DESCRIPTIONThe 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT10 provide the 3-input NAND function.
QUICK REFERENCE DATAGND= 0 V; Tamb =25 °C; tr =tf= 6 ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2× fi + ∑ (CL× VCC2× fO) where:= input frequency in MHz= output frequency in MHz= output load capacitance in pF
VCC= supply voltage in V (CL× VCC2×fo)= sum of outputs For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC− 1.5 V.
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
Philips Semiconductors Product specification
Triple 3-input NAND gate 74HC/HCT10
PIN DESCRIPTION
FUNCTION TABLE
Notes H= HIGH voltage level
Philips Semiconductors Product specification
Triple 3-input NAND gate 74HC/HCT10
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HCGND= 0 V; tr =tf= 6 ns; CL= 50 pF
Philips Semiconductors Product specification
Triple 3-input NAND gate 74HC/HCT10
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
Note to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCTGND= 0 V; tr =tf= 6 ns; CL= 50 pF
AC WAVEFORMS
PACKAGE OUTLINES
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