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74HC7403DPHILIPSN/a1632avai4-Bit x 64-word FIFO register; 3-state
74HCT7403DPHILIPSN/a1728avai4-Bit x 64-word FIFO register; 3-state


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74HC7403D-74HCT7403D
4-Bit x 64-word FIFO register; 3-state

Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
FEATURES
Synchronous or asynchronous
operation 3-state outputs 30 MHz (typical) shift-in and
shift-out rates Readily expandable in word and bit
dimensions Pinning arranged for easy board
layout: input pins directly opposite
output pins Output capability: driver (8 mA) ICC category: LSI.
APPLICATIONS
High-speed disc or tape controller Communications buffer.
GENERAL DESCRIPTION

The 74HC/HCT7403 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no.7A.
The “7403” is an expandable, First-In
First-Out (FIFO) memory organized
as 64 words by 4 bits. A guaranteed
15 MHz data-rate makes it ideal for
high-speed applications. A higher
data-rate can be obtained in
applications where the status flags
are not used (burst-mode).
With separate controls for shift-in (SI)
and shift-out (SO), reading and
writing operations are completely
independent, allowing synchronous
and asynchronous data transfers.
Additional controls include a
master-reset input (MR), an output
enable input (OE) and flags. The
data-in-ready (DIR) and
data-out-ready (DOR) flags indicate
the status of the device.
QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Note
For HC the condition is VI = GND to VCC.
For HCT the condition is VI = GND to VCC −1.5 V.
ORDERING INFORMATION
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
PINNING
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
FUNCTIONAL DESCRIPTION

A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D0 to D3 is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q0 to Q3).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
Expanded format
(see Fig.17)
The DOR and DIR signals are used to
allow the “7403” to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is only possible with
typical devices.
Parallel expansion

Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
Serial expansion

Serial expansion is accomplished by: tying the data outputs of the first
device to the data inputs of the
second device connecting the DOR pin of the first
device to the SI pin of the second
device connecting the SO pin of the first
device to the DIR pin of the second
device.
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not
valid for driver output.
They are replaced by the values given below.
Output capability: driver 8 mA
ICC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HC
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not
valid for driver output.
They are replaced by the values given below.
Output capability: driver 8 mA.
ICC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HCT
Notes to the HCT DC Characteristics
The value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications. To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
UNIT LOAD COEFFICIENT
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full

Notes to Fig.6 DIR initially HIGH; FIFO is prepared for valid data SI set HIGH; data loaded into input stage DIR goes LOW, input stage “busy” SI set LOW; data from first location “ripple through” DIR goes HIGH, status flag indicates FIFO prepared for additional data Repeat process to load 2nd word through to 64th word into FIFO
DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
With FIFO full; SI held HIGH in anticipation of empty location

Notes to Fig.7 FIFO is initially full, shift-in is held HIGH SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Master reset applied with FIFO full

Notes to Fig.8 DIR LOW, output ready HIGH; assume FIFO is full MR pulse LOW; clears FIFO DIR goes HIGH; flag indicates input prepared for valid data DOR goes LOW; flag indicates FIFO empty Qn outputs go LOW (only last bit will be reset).
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