Partno |
Mfg |
Dc |
Qty |
Available | Descript |
74HC73A |
|
N/a |
13 |
|
|
74HC73D ,Dual JK flip-flop with reset; negative-edge triggerGeneral descriptionThe 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-po ..
74HC73D ,Dual JK flip-flop with reset; negative-edge triggerFeaturesn Low-power dissipationn Complies with JEDEC standard no. 7An ESD protection:u HBM JESD22-A ..
74HC73D ,Dual JK flip-flop with reset; negative-edge trigger74HC73Dual JK flip-flop with reset; negative-edge triggerRev. 03 — 12 November 2004 Product data shee ..
74HC74 ,74HC74 Data SheetMAXIMUM RATINGSÎÎSymbol Parameter Value UnitThis device contains protectionV DC Supply Voltage (Ref ..
74HC7403D ,4-Bit x 64-word FIFO register; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74SSTUB32868AZRHR ,28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
74SSTUB32868ZRHR ,28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
74SSTV16859DGGRG4 ,13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 64-TSSOP 0 to 70logic diagram (positive logic)51RESET48CLK49CLK45VREFOne of 13 channels35D1 16Q1A1DC132RQ1BTo 12 Ot ..