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74HC3G07DP
Triple buffer with open-drain outputs
1. General descriptionThe 74HC3G07; 74HCT3G07 is a triple buffer with open-drain outputs. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
2. Features and benefits Wide supply voltage range from 2.0 Vto 6.0V Input levels: For 74HC3G07: CMOS level For 74HCT3G07: TTL level Complies with JEDEC standard no. 7 A High noise immunity Low power dissipation Balanced propagation delays ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs
Rev. 4 — 16 December 2013 Product data sheet
Table 1. Ordering information74HC3G07DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74HCT3G07DP
74HC3G07DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74HCT3G07DC
74HC3G07GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3 2 0.5 mm
SOT996-2
74HCT3G07GD
NXP Semiconductors 74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs
4. Marking[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
6. Pinning information
6.1 Pinning
Table 2. Marking code74HC3G07DP H07
74HCT3G07DP T07
74HC3G07DC H07
74HCT3G07DC T07
74HC3G07GD H07
74HCT3G07GD T07
NXP Semiconductors 74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs
6.2 Pin description
7. Functional description[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
8. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 3. Pin description1A, 2A, 3A 1, 3, 6 data input
GND 4 ground (0 V)
1Y, 2Y, 3Y 7, 5, 2 data output
VCC 8 supply voltage
Table 4. Function table[1]
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 7.0 V
IIK input clamping current VI< 0.5VorVI >VCC + 0.5V [1]- 20 mA
IOK output clamping current VO< 0.5V [1] 20 - mA output voltage active mode [1] 0.5 VCC + 0.5 V
high-impedance mode [1] 0.5 7.0 V output current VO = 0.5 V to 7.0V [1] 25 - mA
ICC supply current [1] -50 mA
IGND ground current [1] 50 - mA
Tstg storage temperature 65 +150 C dynamic power dissipation Tamb = 40Cto +125C [2] -300 mW
NXP Semiconductors 74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditionsVoltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - 6.0 0 - 5.5 V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristicsVoltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb =25 C.
74HC3G07VIH HIGH-level input
voltage
VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level input
voltage
VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOL LOW-level output
voltage = VIH or VIL = 20 A; VCC= 2.0V - 0 0.1 - 0.1 V = 20 A; VCC= 4.5V - 0 0.1 - 0.1 V = 20 A; VCC= 6.0V - 0 0.1 - 0.1 V = 4.0 mA; VCC= 4.5V - 0.15 0.33 - 0.4 V = 5.2 mA; VCC= 6.0V - 0.16 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =6.0V - - 0.1 - 1.0 A
ILO output leakage
current =VIH; VO =VCC or GND - - 5.0 - 10 A
ICC supply current per input pin; VCC =6.0V; =VCCor GND; IO =0A; 10 - 20 A input capacitance - 1.5 - - - pF
NXP Semiconductors 74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs[1] Typical values are measured at Tamb =25C.
11. Dynamic characteristics
74HCT3G07VIH HIGH-level input
voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level input
voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOL LOW-level output
voltage = VIH or VIL = 20 A; VCC= 4.5V - 0 0.1 - 0.1 V = 4.0 mA; VCC= 4.5V - 0.15 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =5.5V - - 1.0 - 1.0 A
ILO output leakage
current =VIH; VO =VCC or GND - - 5.0 - 10 A
ICC supply current per input pin; VCC =5.5V; =VCCor GND; IO =0A; 10 - 20 A
ICC additional supply
current
per input; VCC= 4.5Vto 5.5V; =VCC 2.1 V; IO =0A - 375 - 410 A input capacitance - 1.5 - - - pF
Table 7. Static characteristics …continuedVoltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb =25 C.
Table 8. Dynamic characteristicsVoltages are referenced to GND (ground =0 V); all typical values are measured at Tamb =25 C; for test circuit see Figure7.
74HC3G07tPZL OFF-state to LOW
propagation delayto nY; see Figure6
VCC = 2.0 V - 25 95 - 125 ns
VCC = 4.5 V - 9 19 - 25 ns
VCC = 6.0 V - 7 16 - 20 ns
tPLZ LOW to OFF-state
propagation delayto nY; see Figure6
VCC = 2.0 V - 25 95 - 125 ns
VCC = 4.5 V - 11 23 - 30 ns
VCC = 6.0 V - 10 23 - 26 ns
tTHL HIGH to LOW output
transition time
nY; see Figure6
VCC = 2.0 V - 18 95 - 125 ns
VCC = 4.5 V - 6 19 - 25 ns
VCC = 6.0 V - 5 16 - 20 ns
CPD power dissipation =GNDto VCC [1] -4- - - pF
NXP Semiconductors 74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC 2 fi N + (CL VCC 2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC 2 fo) = sum of outputs.
12. Waveforms
74HCT3G07tPZL OFF-state to LOW
propagation delayto nY; see Figure6
VCC = 4.5 V - 11 27 - 32 ns
tPLZ LOW to OFF-state
propagation delayto nY; see Figure6
VCC = 4.5 V - 10 26 - 31 ns
tTHL HIGH to LOW output
transition time
VCC = 4.5 V; see Figure6 -6 19 - 22 ns
CPD power dissipation
capacitance =GNDto VCC 1.5V [1] -4 - - pF
Table 8. Dynamic characteristics …continuedVoltages are referenced to GND (ground =0 V); all typical values are measured at Tamb =25 C; for test circuit see Figure7.
Table 9. Measurement points74HC3G07 0.5 VCC 0.5 VCC 0.1 VCC
74HCT3G07 1.3 V 1.3 V 0.1 VCC
NXP Semiconductors 74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs
Table 10. Test data 74HC3G07 GND to VCC 6ns 50 pF 1k VCC
74HCT3G07 GND to 3V 6ns 50 pF 1k VCC
