74HC259N-74HCT259PW Fast Delivery |IC PHOENIX CO.,LIMITED

74HCT259PW ,74HC/HCT259; 8-bit addressable latchPin configuration (DIP16, SO16, SSOP16 and Fig 5.
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74HC259N-74HCT259PW
8-bit addressable latch
1. General description
The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7-A.
The 74HC259; 74HCT259 are high-speed 8-bit addressable latches designed for
general-purpose storage applications in digital systems. They are multifunctional devices
capable of storing single-line data in eight addressable latches. They provide a 3-to-8
decoder and multiplexer function with active HIGH outputs (Q0 to Q7). They also
incorporate an active LOW common reset (MR) for resetting all latches as well as an
active LOW enable input (LE).
The 74HC259; 74HCT259 has four modes of operation: Addressable latch mode, in this mode data on the data line (D) is written into the
addressed latch. The addressed latch follows the data input with all non-addressed
latches remaining in their previous states. Memory mode, in this mode all latches remain in their previous states and are
unaffected by the data or address inputs. Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows
the state of the data input (D) with all other outputs in the LOW state. Reset mode, in this mode all outputs are LOW and unaffected by the address inputs
(A0to A2) and data input (D).
When operating the 74HC259; 74HCT259 as an address latch, changing more than one
address bit could impose a transient wrong address. Therefore, this should only be done
while in the Memory mode.
2. Features and benefits Combined demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder Input levels: For 74HC259: CMOS level For 74HCT259: TTL level
74HC259; 74HCT259
8-bit addressable latch
Rev. 5 — 7 August 2012 Product data sheet
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22E exceeds 1000V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74HC259N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT259N
74HC259D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT259D
74HC259DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
74HCT259DB
74HC259PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT259PW
74HC259BQ 40 Cto +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74HCT259BQ
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch
5. Pinning information
5.1 Pinning
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level;= LOW voltage level;= don’t care;= HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;= lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Table 2. Pin description
A0, A1, A2 1, 2, 3 address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output
GND 8 ground (0V) 13 data input 14 latch enable input (active LOW) 15 conditional reset input (active LOW)
VCC 16 supply voltage
Table 3. Function table[1]
Reset (clear) L H X X X X LLLLLLLL
Demultiplexer
(active HIGH 8-channel)
decoder (when D=H) L d L L L Q=d LLLLLLL L d H L L LQ=d LLLLLL L d L H L LLQ=d LLLLL L d H H L LLLQ=d LLLL L d L L H LLLLQ=d LLL L d H L H LLLLLQ=d LL L d L H H LLLLLLQ=dL L d H H H LLLLLLLQ=d
Memory (no action) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7
Addressable latch H L d L L L Q=d q1 q2 q3 q4 q5 q6 q7 d HL L q0 Q=d q2 q3 q4 q5 q6 q7 d L HL q0 q1 Q=d q3 q4 q5 q6 q7 d HHL q0 q1 q2 Q=d q4 q5 q6 q7 Ld LLH q0 q1 q2 q3 Q=d q5 q6 q7 d HL H q0 q1 q2 q3 q4 Q=d q6 q7 d L HH q0 q1 q2 q3 q4 q5 Q=d q7 d HHH q0 q1 q2 q3 q4 q5 q6 Q=d
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch
[1] H= HIGH voltage level; L= LOW voltage level.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70C.
[3] Ptot derates linearly with 8 mW/K above 70C.
[4] Ptot derates linearly with 5.5 mW/K above 60C.
[5] Ptot derates linearly with 4.5 mW/K above 60C.
Table 4. Operating mode select table[1] H Addressable latch mode H Memory mode L Demultiplexer mode Reset mode
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1]- 20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5V [1]- 20 mA output current VO = 0.5 V to VCC +0.5V - 25 mA
ICC supply current - +70 mA
IGND ground current 70 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C
DIP16 package [2]- 750 mW
SO16 package [3]- 500 mW
(T)SSOP16 package [4]- 500 mW
DHVQFN16 package [5]- 500 mW
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch
8. Recommended operating conditions
9. Static characteristics
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V --83 - --ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC259
VIH HIGH-level
input voltage
VCC = 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch input
capacitance
-3.5 - - - - - pF
74HCT259
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0V - 0.15 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =5.5V 0.1 - 1- 1 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
ICC additional
supply current =VCC 2.1 V; IO =0A;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V
pin An, LE - 150 540 - 675 - 735 A
pin D - 120 432 - 540 - 588 A
pin MR - 75 270 - 338 - 368 A input
capacitance
-3.5 - - - - - pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch
10. Dynamic characteristicsTable 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
74HC259
tpd propagation
delay
D to Qn; see Figure6 [2]
VCC = 2.0 V - 58 185 - 230 - 280 ns
VCC = 4.5 V - 21 37 - 46 - 56 ns
VCC = 5.0 V; CL =15pF - 18 - - - - - ns
VCC = 6.0 V - 17 31 - 39 - 48 ns
An to Qn; see Figure7 [2]
VCC = 2.0 V - 58 185 - 230 - 280 ns
VCC = 4.5 V - 21 37 - 46 - 56 ns
VCC = 5.0 V; CL =15pF - 17 - - - - - ns
VCC = 6.0 V - 17 31 - 39 - 48 ns
LE to Qn; see Figure8 [2]
VCC = 2.0 V - 55 170 - 215 - 255 ns
VCC = 4.5 V - 20 34 - 43 - 51 ns
VCC = 5.0 V; CL =15pF - 17 - - - - - ns
VCC = 6.0 V - 16 29 - 37 - 43 ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure9
VCC = 2.0 V - 50 155 - 195 - 235 ns
VCC = 4.5 V - 18 31 - 39 - 47 ns
VCC = 5.0 V; CL =15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 40 ns transition time see Figure8 [3]
VCC = 2.0 V - 19 75 - 95 - 119 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns pulse width LE HIGH or LOW;
see Figure8
VCC = 2.0 V 70 17 - 90 - 105 - ns
VCC = 4.5 V 14 6 - 18 - 21 - ns
VCC = 6.0 V 12 5 - 15 - 18 - ns
MR LOW; see Figure9
VCC = 2.0 V 70 17 - 90 - 105 - ns
VCC = 4.5 V 14 6 - 18 - 21 - ns
VCC = 6.0 V 12 5 - 15 - 18 - ns
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch
tsu set-up time D, An to LE;
see Figure 10 and
Figure11
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns hold time D to LE; see Figure 10
and Figure11
VCC = 2.0 V 0 19 - 0 - 0 - ns
VCC = 4.5 V 0 6- 0 - 0 - ns
VCC = 6.0 V 0 5- 0 - 0 - ns
An to LE; see Figure 10
and Figure11
VCC = 2.0 V 2 11 - 2 - 2 - ns
VCC = 4.5 V 2 4- 2 - 2 - ns
VCC = 6.0 V 2 3- 2 - 2 - ns
CPD power
dissipation
capacitance=1 MHz; =GNDto VCC
[4] -19 - - - - - pF
74HCT259
tpd propagation
delay
D to Qn; see Figure6 [2]
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC = 5.0 V; CL =15pF - 20 - - - - - ns
An to Qn; see Figure7 [2]
VCC = 4.5 V - 25 41 51 62 ns
VCC = 5.0 V; CL =15pF - 20 - - - - - ns
LE to Qn; see Figure8 [2]
VCC = 4.5 V - 22 38 - 48 - 57 ns
VCC = 5.0 V; CL =15pF - 20 - - - - - ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure9
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC = 5.0 V; CL =15pF - 20 - - - - - ns transition time see Figure8 [3]
VCC = 4.5 V - 7 15 - 19 - 22 ns pulse width LE HIGH or LOW;
see Figure8
VCC = 4.5 V 19 11 - 24 - 29 - ns
MR LOW; see Figure9
VCC = 4.5 V 18 10 - 23 - 27 - ns
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch
[1] Typical values are measured at nominal supply voltage (VCC=3.3 V and VCC =5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
11. Waveforms
tsu set-up time D, An to LE;
see Figure 10 and
Figure11
VCC = 4.5 V 17 10 - 21 - 26 - ns hold time D to LE; see Figure 10
and Figure11
VCC = 4.5 V 0 8- 0 - 0 - ns
An to LE; see Figure 10
and Figure11
VCC = 4.5 V 0 4- 0 - 0 - ns
CPD power
dissipation
capacitance=1 MHz; =GNDto VCC  1.5 V
[4] -19 - - - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
NXP Semiconductors 74HC259; 74HCT259
8-bit addressable latch

Partno	Mfg	Dc	Qty	Available	Descript
74HC259N	NXP	N/a	1740	avai	8-bit addressable latch
74HCT259PW	NXP	N/a	50000	avai	74HC/HCT259; 8-bit addressable latch