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74HC253DTOSN/a14avaiDual 4-input multiplexer; 3-state


74HC253D ,Dual 4-input multiplexer; 3-statePin configuration DIP16, SO16 Fig 5.
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74HC253D
Dual 4-input multiplexer; 3-state
1. General description
The 74HC253; 74HCT253 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC253; 74HCT253 provides a dual 4-input multiplexer with 3-state outputs which
selects 2 bits of data from up to four sources selected by common data select inputs (S0,
S1). The two 4-input multiplexer circuits have individual active LOW output enable inputs
(1OE, 2OE).
The 74HC253 and 74HCT253 are the logic implementation of a 2-pole, 4-position switch,
where the position of the switch is determined by the logic levels applied to S0 and S1.
The outputs are forced to a high-impedance OFF-state when nOE is HIGH.
The logic equations for the outputs are:
2. Features and benefits
Non-inverting data path 3-state outputs interface directly with system bus Complies with JEDEC standard no. 7A Common select inputs Separate output enable inputs Input levels: For 74HC253: CMOS level For 74HCT253: TTL level ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125C
74HC253; 74HCT253
Dual 4-input multiplexer; 3-state
Rev. 4 — 12 December 2011 Product data sheet
NXP Semiconductors 74HC253; 74HCT253
Dual 4-input multiplexer; 3-state
3. Applications
Data selectors Data multiplexers
4. Ordering information

5. Functional diagram

Table 1. Ordering information

74HC253N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT253N
74HC253D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
74HCT253D
74HC253DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT253DB
NXP Semiconductors 74HC253; 74HCT253
Dual 4-input multiplexer; 3-state

6. Pinning information
6.1 Pinning

NXP Semiconductors 74HC253; 74HCT253
Dual 4-input multiplexer; 3-state
6.2 Pin description

7. Functional description

[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care; Z= high-impedance OFF-state.
8. Limiting values

Table 2. Pin description

1OE, 2OE 1, 15 output enable inputs (active LOW)
S0, S1 14, 2 data select inputs
1I0, 1I1, 1I2, 1I3 6, 5, 4, 3 data inputs source 1 7 multiplexer output source 1
GND 8 ground (0V) 9 multiplexer output source 2
2I0, 2I1, 2I2, 2I3 10, 11, 12, 13 data inputs source 2
VCC 16 supply voltage
Table 3. Function table[1]
X XXXXH Z L L XXXL L L H XXXL H L XL XXL L L XH XXL H H XXL XL L H XXH XL H H XXXL L L H XXXH L H
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V orVI >VCC +0.5V [1]- 20 mA
IOK output clamping current VO< 0.5 V orVO >VCC +0.5V [1]- 50 mA output current 0.5 V < VO < VCC +0.5V - 35 mA
ICC supply current - 70 mA
IGND ground current 70 - mA
Tstg storage temperature 65 +150 C
NXP Semiconductors 74HC253; 74HCT253
Dual 4-input multiplexer; 3-state

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70C.
[3] Ptot derates linearly with 8 mW/K above 70C.
[4] Ptot derates linearly with 5.5 mW/K above 60C.
9. Recommended operating conditions

10. Static characteristics

Ptot total power dissipation Tamb = 40 C to +125C
DIP16 package [2]- 750 mW
SO16 package [3]- 500 mW
SSOP16 package [4]- 500 mW
Table 4. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC253

VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
NXP Semiconductors 74HC253; 74HCT253
Dual 4-input multiplexer; 3-state

VOH HIGH-level
output voltage =VIHorVIL= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= 6.0 mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= 7.8 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =20 A; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V= 6.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 7.8 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; =VCCor GND;
VCC =6.0V 0.5 - 5.0 - 10.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A input
capacitance
-3.5 - pF
74HCT253

VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= 20A 4.4 4.5 - 4.4 - 4.4 - V=6 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20A - 0 0.1 - 0.1 - 0.1 V= 6.0 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V 0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current =VIHor VIL; VCC =5.5V; =VCC or GND per input
pin; other inputs at VCC or
GND; IO =0A 0.5 - 5.0 - 10 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC253; 74HCT253
Dual 4-input multiplexer; 3-state
11. Dynamic characteristics

ICC additional
supply current =VCC 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
per input pin; 1In, 2In
inputs 40 144 - 180 - 196 A
per input pin; nOE input - 110 396 - 495 - 539 A
per input pin; Sn input - 110 396 - 495 - 539 A input
capacitance
-3.5 - pF
Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics

Voltages are referenced to GND (ground=0 V); For test circuit see Figure8.
74HC253

tpd propagation delay 1lnto1Y or 2ln to 2Y;
see Figure6
[1]
VCC = 2.0 V 55 175 220 265 ns
VCC = 4.5 V 20 35 44 53 ns
VCC = 5.0 V; CL = 15 pF 17 - - - ns
VCC = 6.0 V 16 30 37 45 nsto nY; see Figure6
VCC = 2.0 V 58 175 220 265 ns
VCC = 4.5 V 21 35 44 53 ns
VCC = 5.0 V; CL = 15 pF 18 - - - ns
VCC = 6.0 V 17 30 37 45 ns
ten enable time nOE to nY; see Figure7 [2]
VCC = 2.0 V 30 100 125 150 ns
VCC = 4.5 V 11 20 25 30 ns
VCC = 6.0 V 9 17 21 26 ns
tdis disable time nOE to nY; see Figure7 [3]
VCC = 2.0 V 41 150 190 225 ns
VCC = 4.5 V 15 30 38 45 ns
VCC = 6.0 V 12 26 33 38 ns
NXP Semiconductors 74HC253; 74HCT253
Dual 4-input multiplexer; 3-state

[1] tpd is the same as tPHL, tPLH.
[2] ten is the same as tPZH, tPZL.
[3] tdis is the same as tPHZ, tPLZ.
[4] tt is the same as tTHL, tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2 fo) = sum of outputs. transition time see Figure6 [4]
VCC = 2.0 V 14 60 75 90 ns
VCC = 4.5 V 5 12 15 18 ns
VCC = 6.0 V 4 10 13 15 ns
CPD power dissipation
capacitance
per multiplexer; =GNDto VCC
[5] 55 - pF
74HCT253

tpd propagation delay 1lnto1Y or 2ln to 2Y;
see Figure6
[1]
VCC = 4.5 V 20 38 48 57 ns
VCC = 5.0 V; CL = 15 pF 17 - - ns to nY; see Figure6
VCC = 4.5 V 22 40 50 60 ns
VCC = 5.0 V; CL = 15 pF 19 - ns
ten enable time nOE to nY; VCC= 4.5 V; see
Figure7
[2] 14 30 38 45 ns
tdis disable time nOE to nY; VCC =4.5 V;
see Figure7
[3] 13 30 38 45 ns transition time VCC = 4.5 V; see Figure6 512 15 18 ns
CPD power dissipation
capacitance
per multiplexer; =GNDto VCC
[5] 55 - pF
Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground=0 V); For test circuit see Figure8.
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