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74HC132HITN/a381avaiQuad 2-input NAND Schmitt trigger


74HC132D ,74HC/HCT132; Quad 2-input NAND Schmitt triggerPin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.FUNCTION TABLEINPUTS OUTPUTnA nB nY ..
74HC132N ,Quad 2-input NAND Schmitt triggerPin configuration DIP14, SO14 and (T)SSOP146.2 Pin description Table 2. Pin descriptionSymbol Pin D ..
74HC132PW ,74HC/HCT132; Quad 2-input NAND Schmitt triggerPin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.FUNCTION TABLEINPUTS OUTPUTnA nB nY ..
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74HC132
Quad 2-input NAND Schmitt trigger
74HC132
Quad 2−Input NAND Gate
with Schmitt−Trigger Inputs
High−Performance Silicon−Gate CMOS

The 74HC132 is identical in pinout to the LS132. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
The HC132 can be used to enhance noise immunity or to square up
slowly changing waveforms.
Features
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 �A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A• ESD Performance: HBM � 2000 V; Machine Model � 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These are Pb−Free Devices
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