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74HC112D ,dual JK flip-flop with set and reset; negative-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
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74HC112D-74HCT112D-74HCT112N
74HC112;74HCT112; dual JK flip-flop with set and reset; negative-edge trigger

Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger 74HC/HCT112
FEATURES
Asynchronous set and reset Output capability: standard ICC category: flip-flops
GENERAL DESCRIPTION

The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nSD) and reset (nRD) inputs.
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA

GND= 0 V; Tamb =25 °C; tr =tf= 6 ns
Notes
CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi +∑ (CL× VCC2× fo) where:= input frequency in MHz= output frequency in MHz (CL× VCC2×fo)= sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC− 1.5 V
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger 74HC/HCT112
ORDERING INFORMATION
PIN DESCRIPTION
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger 74HC/HCT112
FUNCTION TABLE
Note
If nSD and nRD simultaneously go from LOW to HIGH, the output states will
be unpredictable.= HIGH voltage level= HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition= LOW voltage level= LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition= lower case letters indicate the state of the referenced output one set-up
time prior to the HIGH-to-LOW CP transition= don’t care= HIGH-to-LOW CP transition
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger 74HC/HCT112
DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger 74HC/HCT112
AC CHARACTERISTICS FOR 74HC

GND= 0 V; tr =tf= 6 ns; CL= 50 pF
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger 74HC/HCT112
DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Note to HCT types

The value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger 74HC/HCT112
AC CHARACTERISTICS FOR 74HCT

GND= 0 V; tr =tf= 6 ns; CL= 50 pF
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