74F299SJX , Octal Universal Shift/Storage Register with Common Parallel I/O PinsapplicationsQ , are provided to allow easy serial cascading. A separate7 Guaranteed 4000V minimum E ..
74F299SJX , Octal Universal Shift/Storage Register with Common Parallel I/O PinsFunctional Description Logic DiagramThe 74F299 contains eight edge-triggered D-type flip-flopsand t ..
74F30 ,8-Input NAND GateGeneral DescriptionThis device contains a single gate, which performs thelogic NAND function. Order ..
74F3038 ,Quad 2-input NAND 30Ohm driver (open collector)
74F30PC ,8-Input NAND GateGeneral DescriptionThis device contains a single gate, which performs thelogic NAND function. Order ..
74F30SCX ,8-Input NAND GateGeneral DescriptionThis device contains a single gate, which performs thelogic NAND function. Order ..
74HCU04N ,Hex inverterLogic diagram (one inverter)5. Pinning information 74HCU04terminal 1index area74HCU041Y 2 13 6A1 14 ..
74HCU04PW ,74HCU04; Hex inverterGENERAL DESCRIPTIONThe 74HCU04 is a high-speed Si-gate CMOS device and is pin compatible with low p ..
74HCU04PW ,74HCU04; Hex inverterFEATURES• Output capability: standard• I category: SSICC
74HCU04PW ,74HCU04; Hex inverterGeneral descriptionThe 74HCU04 is a hex unbuffered inverter. Inputs include clamp diodes. This enab ..
74LCX00 ,Low Voltage Quad 2-Input NAND Gate with 5V Tolerant InputsFeaturesThe LCX00 contains four 2-input NAND gates. The inputs
74F299SJX
Octal Universal Shift/Storage Register with Common Parallel I/O Pins
74F299 Octal Universal Shift/Storage Register April 1988 Revised August 1999 74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins General Description Features The 74F299 is an 8-bit universal shift/storage register with � Common parallel I/O for reduced pin count 3-STATE outputs. Four modes of operation are possible: � Additional serial inputs and outputs for expansion hold (store), shift left, shift right and load data. The parallel � Four operating modes: shift left, shift right, load and load inputs and flip-flop outputs are multiplexed to reduce store the total number of package pins. Additional outputs, Q – 0 � 3-STATE outputs for bus-oriented applications Q , are provided to allow easy serial cascading. A separate 7 � Guaranteed 4000V minimum ESD protection active LOW Master Reset is used to reset the register. Ordering Code: Order Number Package Number Package Description 74F299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F299SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 DS009515
