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74F109PCFSCN/a3000avaiDual JK# Positive Edge-Triggered Flip-Flop
74F109SCFAIRCHILDN/a3avaiDual JK Positive Edge-Triggered Flip-Flop
74F109SCXN/a2500avaiDual JK# Positive Edge-Triggered Flip-Flop
74F109SJFAIRCHILDN/a920avaiDual JK# Positive Edge-Triggered Flip-Flop


74F109PC ,Dual JK# Positive Edge-Triggered Flip-FlopGeneral DescriptionLOW input to S sets Q to HIGH levelDThe F109 consists of two high-speed, complet ..
74F109SC ,Dual JK Positive Edge-Triggered Flip-FlopGeneral DescriptionLOW input to S sets Q to HIGH levelDThe F109 consists of two high-speed, complet ..
74F109SCX ,Dual JK# Positive Edge-Triggered Flip-Flop74F109 Dual JK Positive Edge-Triggered Flip-FlopApril 1988Revised September 200074F109Dual JK Posit ..
74F109SJ ,Dual JK# Positive Edge-Triggered Flip-FlopGeneral DescriptionLOW input to S sets Q to HIGH levelDThe F109 consists of two high-speed, complet ..
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74F109PC-74F109SC-74F109SCX-74F109SJ
Dual JK# Positive Edge-Triggered Flip-Flop
74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop Asynchronous Inputs: General Description LOW input to S sets Q to HIGH level D The F109 consists of two high-speed, completely indepen- dent transition clocked JK flip-flops. The clocking operation LOW input to C sets Q to LOW level D is independent of rise and fall times of the clock waveform. Clear and Set are independent of clock The JK design allows operation as a D-type flip-flop (refer Simultaneous LOW on C and S makes D D to F74 data sheet) by connecting the J and K inputs. both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009471
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