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74AUP1G74DC
Low-power D-type flip-flop with set and reset; positive-edge trigger
1. General description
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type
flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 0.8Vto 3.6V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8Vto 1.3V) JESD8-11 (0.9Vto 1.65V) JESD8-7 (1.2Vto 1.95V) JESD8-5 (1.8Vto 2.7V) JESD8-B (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 9 — 6 January 2014 Product data sheet
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74AUP1G74DC 40 C to +125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74AUP1G74GT 40 C to +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 1 1.95 0.5 mm
SOT833-1
74AUP1G74GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74AUP1G74GD 40 Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74AUP1G74GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
74AUP1G74GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.21.0 0.35 mm
SOT1116
74AUP1G74GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74AUP1G74DC p74
74AUP1G74GT p74
74AUP1G74GF 54
74AUP1G74GD p74
74AUP1G74GM p74
74AUP1G74GN 54
74AUP1G74GS 54
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
6. Pinning information
6.1 Pinning
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care.
Table 3. Pin description 1 7 clock input 2 6 data input 3 5 complement output
GND 4 4 ground (0V) 5 3 true output 6 2 asynchronous reset input (active LOW) 7 1 asynchronous set input (active LOW)
VCC 8 8 supply voltage
Table 4. Function table for asynchronous operation[1] H XXH L L XXL H L XXH H
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
[1] H= HIGH voltage level;= LOW voltage level;= don’t care;= LOW-to-HIGH CP transition;
Qn+1= state after the next LOW-to-HIGH CP transition.
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Function table for synchronous operation[1]  LLH  HHL
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +4.6 V
IOK output clamping current VO <0V 50 - mA output voltage Active mode and Power-down mode [1] 0.5 +4.6 V output current VO =0Vto VCC - 20 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [2] -250 mW
Table 7. Operating conditions
VCC supply voltage 0.8 3.6 V input voltage 0 3.6 V output voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 3.6 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC= 0.8 V to 3.6V - 200 ns/V
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
10. Static characteristicsTable 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = 25C
VIH HIGH-level input voltage VCC = 0.8V 0.70  VCC -- V
VCC = 0.9 V to 1.95V 0.65  VCC -- V
VCC = 2.3 V to 2.7V 1.6 - - V
VCC = 3.0 V to 3.6V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8V - - 0.30  VCCV
VCC = 0.9 V to 1.95V - - 0.35  VCCV
VCC = 2.3 V to 2.7V - - 0.7 V
VCC = 3.0 V to 3.6V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1V 0.75  VCC -- V
IO = 1.7 mA; VCC = 1.4V 1.11 - - V
IO = 1.9 mA; VCC = 1.65V 1.32 - - V
IO = 2.3 mA; VCC = 2.3V 2.05 - - V
IO = 3.1 mA; VCC = 2.3V 1.9 - - V
IO = 2.7 mA; VCC = 3.0V 2.72 - - V
IO = 4.0 mA; VCC = 3.0V 2.6 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4V - - 0.31 V
IO = 1.9 mA; VCC = 1.65V - - 0.31 V
IO = 2.3 mA; VCC = 2.3V - - 0.31 V
IO = 3.1 mA; VCC = 2.3V - - 0.44 V
IO = 2.7 mA; VCC = 3.0V - - 0.31 V
IO = 4.0 mA; VCC = 3.0V - - 0.44 V input leakage current VI = GND to 3.6 V; VCC = 0V to 3.6V - - 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0V - - 0.2 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6V;
VCC =0Vto0.2V 0.2 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8 V to 3.6V 0.5 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3 V; per pin
[1] -- 40 A input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC -0.6 -pF output capacitance VO = GND; VCC = 0V -1.3 -pF
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Tamb = 40 C to +85C
VIH HIGH-level input voltage VCC = 0.8V 0.70  VCC -- V
VCC = 0.9 V to 1.95V 0.65  VCC -- V
VCC = 2.3 V to 2.7V 1.6 - - V
VCC = 3.0 V to 3.6V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8V - - 0.30  VCCV
VCC = 0.9 V to 1.95V - - 0.35  VCCV
VCC = 2.3 V to 2.7V - - 0.7 V
VCC = 3.0 V to 3.6V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1V 0.7  VCC -- V
IO = 1.7 mA; VCC = 1.4V 1.03 - - V
IO = 1.9 mA; VCC = 1.65V 1.30 - - V
IO = 2.3 mA; VCC = 2.3V 1.97 - - V
IO = 3.1 mA; VCC = 2.3V 1.85 - - V
IO = 2.7 mA; VCC = 3.0V 2.67 - - V
IO = 4.0 mA; VCC = 3.0V 2.55 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6V - - 0.1 V
IO = 1.1 mA; VCC = 1.1V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4V - - 0.37 V
IO = 1.9 mA; VCC = 1.65V - - 0.35 V
IO = 2.3 mA; VCC = 2.3V - - 0.33 V
IO = 3.1 mA; VCC = 2.3V - - 0.45 V
IO = 2.7 mA; VCC = 3.0V - - 0.33 V
IO = 4.0 mA; VCC = 3.0V - - 0.45 V input leakage current VI = GND to 3.6 V; VCC = 0V to 3.6V - - 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0V - - 0.5 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6V;
VCC =0Vto0.2V 0.6 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8 V to 3.6V 0.9 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3 V; per pin
[1] -- 50 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
[1] One input at VCC  0.6 V, other input at VCC or GND.
Tamb = 40 C to +125C
VIH HIGH-level input voltage VCC = 0.8V 0.75  VCC -- V
VCC = 0.9 V to 1.95V 0.70  VCC -- V
VCC = 2.3 V to 2.7V 1.6 - - V
VCC = 3.0 V to 3.6V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8V - - 0.25  VCCV
VCC = 0.9 V to 1.95V - - 0.30  VCCV
VCC = 2.3 V to 2.7V - - 0.7 V
VCC = 3.0 V to 3.6V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6V VCC  0.11- - V
IO = 1.1 mA; VCC = 1.1V 0.6  VCC -- V
IO = 1.7 mA; VCC = 1.4V 0.93 - - V
IO = 1.9 mA; VCC = 1.65V 1.17 - - V
IO = 2.3 mA; VCC = 2.3V 1.77 - - V
IO = 3.1 mA; VCC = 2.3V 1.67 - - V
IO = 2.7 mA; VCC = 3.0V 2.40 - - V
IO = 4.0 mA; VCC = 3.0V 2.30 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6V - - 0.11 V
IO = 1.1 mA; VCC = 1.1V - - 0.33  VCCV
IO = 1.7 mA; VCC = 1.4V - - 0.41 V
IO = 1.9 mA; VCC = 1.65V - - 0.39 V
IO = 2.3 mA; VCC = 2.3V - - 0.36 V
IO = 3.1 mA; VCC = 2.3V - - 0.50 V
IO = 2.7 mA; VCC = 3.0V - - 0.36 V
IO = 4.0 mA; VCC = 3.0V - - 0.50 V input leakage current VI = GND to 3.6 V; VCC = 0V to 3.6V - - 0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0V - - 0.75 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6V;
VCC =0Vto0.2V 0.75 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8 V to 3.6V 1.4 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3 V; per pin
[1] -- 75 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
11. Dynamic characteristicsTable 9. Dynamic characteristics
Voltages are referenced to GND (ground=0 V); for test circuit see Figure 10.
CL = 5pF
tpd propagation
delaytoQ, Q; see Figure8 [2]
VCC = 0.8V - 25.4 - - - - - ns
VCC = 1.1 V to 1.3V 2.9 6.7 14.0 2.6 14.2 2.6 14.2 ns
VCC = 1.4 V to 1.6V 2.4 4.5 7.6 2.3 8.3 2.3 8.6 ns
VCC = 1.65 V to 1.95V 1.9 3.5 5.7 1.7 6.5 1.7 6.8 ns
VCC = 2.3 V to 2.7V 1.7 2.6 3.8 1.4 4.4 1.4 4.7 ns
VCC = 3.0 V to 3.6V 1.5 2.2 3.1 1.2 3.4 1.2 3.7 ns
SDtoQ, Q; see Figure9 [2]
VCC = 0.8V - 19.6 - - - - - ns
VCC = 1.1 V to 1.3V 2.7 5.6 11.0 2.5 11.4 2.5 11.5 ns
VCC = 1.4 V to 1.6V 2.4 4.0 6.3 2.2 6.9 2.2 7.3 ns
VCC = 1.65 V to 1.95V 2.0 3.3 4.9 1.7 5.6 1.7 5.9 ns
VCC = 2.3 V to 2.7V 1.9 2.7 3.7 1.7 4.0 1.7 4.2 ns
VCC = 3.0 V to 3.6V 1.8 2.5 3.2 1.5 3.6 1.5 3.8 ns
RDtoQ,Q; see Figure9 [2]
VCC = 0.8V - 19.2 - - - - - ns
VCC = 1.1 V to 1.3V 2.6 5.5 11.0 2.5 11.3 2.5 11.5 ns
VCC = 1.4 V to 1.6V 2.3 3.9 6.3 2.2 6.8 2.2 7.3 ns
VCC = 1.65 V to 1.95V 1.9 3.2 5.0 1.8 5.6 1.8 5.9 ns
VCC = 2.3 V to 2.7V 1.9 2.6 3.6 1.7 4.1 1.7 4.3 ns
VCC = 3.0 V to 3.6V 1.8 2.4 3.3 1.5 3.6 1.5 3.8 ns
fmax maximum
frequency
CP; see Figure8
VCC = 0.8V - 53 - - - - - MHz
VCC = 1.1 V to 1.3V - 203 - 170 - 170 - MHz
VCC = 1.4 V to 1.6V - 347 - 310 - 300 - MHz
VCC = 1.65 V to 1.95V - 435 - 400 - 390 - MHz
VCC = 2.3 V to 2.7V - 550 - 490 - 480 - MHz
VCC = 3.0 V to 3.6V - 619 - 550 - 510 - MHz
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
CL = 10pF
tpd propagation
delaytoQ, Q; see Figure8 [2]
VCC = 0.8V - 28.9 - - - - - ns
VCC = 1.1 V to 1.3V 3.1 7.5 15.8 2.9 16.1 2.9 16.1 ns
VCC = 1.4 V to 1.6V 2.7 5.1 8.7 2.4 9.4 2.4 9.8 ns
VCC = 1.65 V to 1.95V 2.5 4.1 6.5 2.2 7.2 2.2 7.6 ns
VCC = 2.3 V to 2.7V 2.0 3.2 4.6 1.8 5.3 1.8 5.6 ns
VCC = 3.0 V to 3.6V 1.8 2.8 3.8 1.6 4.1 1.6 4.4 ns
SDtoQ, Q; see Figure9 [2]
VCC = 0.8V - 23.2 - - - - - ns
VCC = 1.1 V to 1.3V 2.9 6.5 12.9 2.8 13.3 2.8 13.5 ns
VCC = 1.4 V to 1.6V 2.7 4.6 7.5 2.3 7.9 2.3 8.3 ns
VCC = 1.65 V to 1.95V 2.6 3.9 5.6 2.3 6.3 2.3 6.6 ns
VCC = 2.3 V to 2.7V 2.3 3.2 4.4 2.0 4.8 2.0 5.2 ns
VCC = 3.0 V to 3.6V 2.2 3.0 3.9 1.9 4.2 1.9 4.4 ns
RDtoQ,Q; see Figure9 [2]
VCC = 0.8V - 22.7 - - - - - ns
VCC = 1.1 V to 1.3V 2.8 6.4 12.8 2.7 13.2 2.7 13.4 ns
VCC = 1.4 V to 1.6V 2.6 4.5 7.5 2.3 8.1 2.3 8.4 ns
VCC = 1.65 V to 1.95V 2.5 3.3 5.8 2.3 6.3 2.3 6.7 ns
VCC = 2.3 V to 2.7V 2.2 3.2 4.4 2.0 4.9 2.0 5.2 ns
VCC = 3.0 V to 3.6V 2.0 2.9 4.0 1.9 4.3 1.9 4.5 ns
fmax maximum
frequency
CP; see Figure8
VCC = 0.8V - 52 - - - - - MHz
VCC = 1.1 V to 1.3V - 192 - 150 - 150 - MHz
VCC = 1.4 V to 1.6V - 324 - 280 - 230 - MHz
VCC = 1.65 V to 1.95V - 421 - 310 - 250 - MHz
VCC = 2.3 V to 2.7V - 486 - 370 - 360 - MHz
VCC = 3.0 V to 3.6V - 550 - 410 - 360 - MHz
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit see Figure 10.
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
CL = 15pF
tpd propagation
delaytoQ, Q; see Figure8 [2]
VCC = 0.8V - 32.4 - - - - - ns
VCC = 1.1 V to 1.3V 3.5 8.3 17.6 3.3 17.8 3.3 18.0 ns
VCC = 1.4 V to 1.6V 3.2 5.6 9.5 2.8 10.5 2.8 11.1 ns
VCC = 1.65 V to 1.95V 2.7 4.6 7.2 2.5 8.1 2.5 8.6 ns
VCC = 2.3 V to 2.7V 2.4 3.6 5.2 2.2 5.8 2.2 6.2 ns
VCC = 3.0 V to 3.6V 2.2 3.2 4.4 2.0 4.9 2.0 5.2 ns
SDtoQ, Q; see Figure9 [2]
VCC = 0.8V - 26.7 - - - - - ns
VCC = 1.1 V to 1.3V 3.3 7.3 14.7 3.1 15.2 3.1 15.4 ns
VCC = 1.4 V to 1.6V 3.2 5.2 8.3 2.9 9.0 2.9 9.5 ns
VCC = 1.65 V to 1.95V 2.8 4.3 6.4 2.5 7.1 2.5 7.5 ns
VCC = 2.3 V to 2.7V 2.8 3.7 5.1 2.2 5.5 2.2 5.8 ns
VCC = 3.0 V to 3.6V 2.5 3.5 4.6 2.4 5.0 2.4 5.2 ns
RDtoQ,Q; see Figure9 [2]
VCC = 0.8V - 26.1 - - - - - ns
VCC = 1.1 V to 1.3V 3.2 7.2 14.5 3.1 15.0 3.1 15.2 ns
VCC = 1.4 V to 1.6V 3.1 5.1 8.4 2.7 9.2 2.7 9.7 ns
VCC = 1.65 V to 1.95V 2.7 4.3 6.5 2.6 7.3 2.6 7.7 ns
VCC = 2.3 V to 2.7V 2.6 3.6 5.0 2.4 5.5 2.4 5.8 ns
VCC = 3.0 V to 3.6V 2.4 3.4 4.6 2.3 5.0 2.3 5.2 ns
fmax maximum
frequency
CP; see Figure8
VCC = 0.8V - 50 - - - - - MHz
VCC = 1.1 V to 1.3V - 181 - 120 - 120 - MHz
VCC = 1.4 V to 1.6V - 301 - 190 - 160 - MHz
VCC = 1.65 V to 1.95V - 407 - 240 - 190 - MHz
VCC = 2.3 V to 2.7V - 422 - 300 - 270 - MHz
VCC = 3.0 V to 3.6V - 481 - 320 - 300 - MHz
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit see Figure 10.
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
CL = 30pF
tpd propagation
delaytoQ, Q; see Figure8 [2]
VCC = 0.8V - 42.7 - - - - - ns
VCC = 1.1 V to 1.3V 4.2 10.6 22.5 4.0 23.0 4.0 23.3 ns
VCC = 1.4 V to 1.6V 3.7 7.2 12.0 3.7 13.3 3.7 14.0 ns
VCC = 1.65 V to 1.95V 3.5 5.8 9.2 3.4 10.4 3.4 11.0 ns
VCC = 2.3 V to 2.7V 3.3 4.7 6.6 3.0 7.3 3.0 7.8 ns
VCC = 3.0 V to 3.6V 3.0 4.3 5.8 2.8 6.8 2.8 7.3 ns
SDtoQ, Q; see Figure9 [2]
VCC = 0.8V - 37.0 - - - - - ns
VCC = 1.1 V to 1.3V 4.0 9.5 19.8 3.8 20.8 3.8 21.1 ns
VCC = 1.4 V to 1.6V 3.8 6.7 10.9 3.7 12.0 3.7 12.7 ns
VCC = 1.65 V to 1.95V 3.7 5.6 8.4 3.5 9.3 3.5 9.9 ns
VCC = 2.3 V to 2.7V 3.7 4.8 6.6 3.2 7.2 3.2 7.6 ns
VCC = 3.0 V to 3.6V 3.4 4.6 6.0 3.1 6.8 3.1 7.1 ns
RDtoQ,Q; see Figure9 [2]
VCC = 0.8V - 36.4 - - - - - ns
VCC = 1.1 V to 1.3V 3.9 9.4 19.5 3.8 20.2 3.8 20.5 ns
VCC = 1.4 V to 1.6V 3.6 6.6 10.9 3.7 12.0 3.7 12.6 ns
VCC = 1.65 V to 1.95V 3.5 5.5 8.5 3.5 9.5 3.5 10.1 ns
VCC = 2.3 V to 2.7V 3.5 4.7 6.5 3.2 7.1 3.2 7.6 ns
VCC = 3.0 V to 3.6V 3.3 4.4 6.1 3.1 7.1 3.1 7.5 ns
fmax maximum
frequency
CP; see Figure8
VCC = 0.8V - 28 - - - - - MHz
VCC = 1.1 V to 1.3V - 145 - 70 - 70 - MHz
VCC = 1.4 V to 1.6V - 185 - 120 - 110 - MHz
VCC = 1.65 V to 1.95V - 270 - 150 - 120 - MHz
VCC = 2.3 V to 2.7V - 290 - 190 - 170 - MHz
VCC = 3.0 V to 3.6V - 315 - 200 - 190 - MHz
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit see Figure 10.
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
CL = 5 pF, 10 pF, 15 pF and 30pF
tsu set-up time Dto CP HIGH;
see Figure8
VCC = 0.8V - 3.4 - - - - - ns
VCC = 1.1 V to 1.3V - 0.6 - 1.2 - 1.2 - ns
VCC = 1.4 V to 1.6V - 0.3 - 0.6 - 0.6 - ns
VCC = 1.65 V to 1.95V - 0.4 - 0.5 - 0.5 - ns
VCC = 2.3 V to 2.7V - 0.2 - 0.4 - 0.4 - ns
VCC = 3.0 V to 3.6V - 0.3 - 0.4 - 0.4 - ns
DtoCP LOW;
see Figure8
VCC = 0.8V - 3.0 - - - - - ns
VCC = 1.1 V to 1.3V - 0.5 - 1.2 - 1.2 - ns
VCC = 1.4 V to 1.6V - 0.3 - 0.7 - 0.7 - ns
VCC = 1.65 V to 1.95V - 0.4 - 0.7 - 0.7 - ns
VCC = 2.3 V to 2.7V - 0.5 - 0.7 - 0.7 - ns
VCC = 3.0 V to 3.6V - 0.6 - 0.8 - 0.8 - ns hold time D to CP; see Figure8
VCC = 0.8V - 1.9 - - - - - ns
VCC = 1.1 V to 1.3V - 0.3 - 0.5 - 0.5 - ns
VCC = 1.4 V to 1.6V - 0.2 - 0.2 - 0.2 - ns
VCC = 1.65 V to 1.95V - 0.2 - 0.1 - 0.1 - ns
VCC = 2.3 V to 2.7V - 0.2 - 0.1 - 0.1 - ns
VCC = 3.0 V to 3.6V - 0.2 - 0.1 - 0.1 - ns
trec recovery time RD; see Figure9
VCC = 1.1 V to 1.3V - 0.5 - 0.9 - 0.9 - ns
VCC = 1.4 V to 1.6V - 0.2 - 0.6 - 0.6 - ns
VCC = 1.65 V to 1.95V - 0.2 - 0.4 - 0.4 - ns
VCC = 2.3 V to 2.7V - 0.1 - 0.1 - 0.1 - ns
VCC = 3.0 V to 3.6V - 0.1 - 0.1 - 0.1 - ns
SD; see Figure9
VCC = 1.1 V to 1.3V - 0.5 - 0.3 - 0.3 - ns
VCC = 1.4 V to 1.6V - 0.4 - 0.1 - 0.1 - ns
VCC = 1.65 V to 1.95V - 0.3 - 0 - 0 - ns
VCC = 2.3 V to 2.7V - 0.2 - 0.1 - 0.1 - ns
VCC = 3.0 V to 3.6V - 0.1 - 0.1 - 0.1 - ns
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit see Figure 10.
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs. pulse width CP HIGH or LOW;
see Figure8
VCC = 1.1 V to 1.3V - 2.1 - 2.7 - 2.7 - ns
VCC = 1.4 V to 1.6V - 1.1 - 1.5 - 1.5 - ns
VCC = 1.65 V to 1.95V - 0.9 - 1.6 - 1.6 - ns
VCC = 2.3 V to 2.7V - 0.6 - 1.7 - 1.7 - ns
VCC = 3.0 V to 3.6V - 0.6 - 1.9 - 1.9 - ns
SD or RD LOW;
see Figure9
VCC = 1.1 V to 1.3V - 4.2 - 11.3 - 11.5 - ns
VCC = 1.4 V to 1.6V - 2.3 - 6.2 - 6.4 - ns
VCC = 1.65 V to 1.95V - 1.8 - 4.8 - 5.0 - ns
VCC = 2.3 V to 2.7V - 1.2 - 3.3 - 3.5 - ns
VCC = 3.0 V to 3.6V - 1.1 - 2.6 - 2.8 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; =GNDto VCC
[3]
VCC = 0.8V - 2.8 - - - - - pF
VCC = 1.1 V to 1.3V - 2.9 - - - - - pF
VCC = 1.4 V to 1.6V - 3.0 - - - - - pF
VCC = 1.65 V to 1.95V - 3.0 - - - - - pF
VCC = 2.3 V to 2.7V - 3.5 - - - - - pF
VCC = 3.0 V to 3.6V - 3.9 - - - - - pF
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit see Figure 10.

Partno	Mfg	Dc	Qty	Available	Descript
74AUP1G74DC	NXP	N/a	100	avai	Low-power D-type flip-flop with set and reset; positive-edge trigger