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74AUP1G373GF-74AUP1G373GW
Low-power D-type transparent latch; 3-state
1. General descriptionThe 74AUP1G373 provides the single D-type transparent latch with 3-state output. While
the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is
LOW, the latch stores the information that was present at the D-input one set-up time
preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of
the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the
high-impedance OFF-state. Operation of input pin OE does not affect the state of the
latch.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits Wide supply voltage range from 0.8 Vto 3.6V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 Vto 1.3 V) JESD8-11 (0.9 Vto 1.65V) JESD8-7 (1.2 Vto 1.95V) JESD8-5 (1.8 Vto 2.7V) JESD8-B (2.7 Vto 3.6V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
74AUP1G373
Low-power D-type transparent latch; 3-state
Rev. 6 — 4 July 2012 Product data sheet
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state
3. Ordering information
4. Marking[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information74AUP1G373GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74AUP1G373GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm
SOT886
74AUP1G373GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 11 0.5 mm
SOT891
74AUP1G373GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74AUP1G373GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
Table 2. Marking74AUP1G373GW aW
74AUP1G373GM aW
74AUP1G373GF aW
74AUP1G373GN aW
74AUP1G373GS aW
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description[1] H= HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition;= LOW voltage level;= LOW voltage level one setup time prior to the HIGH-to-LOW LE transition;= Don’t care;= high-impedance OFF-state.
Table 3. Pin description 1 latch enable input (active HIGH)
GND 2 ground (0V) 3 data input 4 latch output
VCC 5 supply voltage 6 output enable input (active LOW)
Table 4. Function table[1]Enable and read register (transparent
mode) L L L HHH H
Latch and read register L L l L L LhH H
Latch register and disable outputs H X X X Z
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state
8. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
10. Static characteristics
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +4.6 V
IOK output clamping current VO <0V 50 - mA output voltage Active mode and Power-down mode [1] 0.5 +4.6 V output current VO =0 VtoVCC - 20 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [2] -250 mW
Table 6. Recommended operating conditionsVCC supply voltage 0.8 3.6 V input voltage 0 3.6 V output voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 3.6 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC= 0.8 V to 3.6V - 200 ns/V
Table 7. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = 25 CVIH HIGH-level input voltage VCC = 0.8 V 0.70 VCC -- V
VCC = 0.9 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 VCCV
VCC = 0.9 V to 1.95 V - - 0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-stateVOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.75 VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.11 - - V
IO = 1.9 mA; VCC = 1.65 V 1.32 - - V
IO = 2.3 mA; VCC = 2.3 V 2.05 - - V
IO = 3.1 mA; VCC = 2.3 V 1.9 - - V
IO = 2.7 mA; VCC = 3.0 V 2.72 - - V
IO = 4.0 mA; VCC = 3.0 V 2.6 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A
IOZ OFF-state output current VI = VIH or VIL; VO = 0 V to 3.6V;
VCC = 0 V to 3.6 V 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6V;
VCC=0Vto 0.2 V 0.2 A
ICC supply current VI = GND or VCC; IO =0A;
VCC= 0.8 V to 3.6 V 0.5 A
ICC additional supply current VI = VCC 0.6 V; IO =0A;
VCC =3.3V
[1] -- 40 A input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC -0.8 -pF output capacitance output enabled; VO = GND; VCC = 0 V - 1.7 - pF
output disabled; VCC = 0 V to 3.6 V;
VO = GND or VCC
-1.5 -pF
Tamb = 40 C to +85C
VIH HIGH-level input voltage VCC = 0.8 V 0.70 VCC -- V
VCC = 0.9 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 VCCV
VCC = 0.9 V to 1.95 V - - 0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
Table 7. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-stateVOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.7 VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.03 - - V
IO = 1.9 mA; VCC = 1.65 V 1.30 - - V
IO = 2.3 mA; VCC = 2.3 V 1.97 - - V
IO = 3.1 mA; VCC = 2.3 V 1.85 - - V
IO = 2.7 mA; VCC = 3.0 V 2.67 - - V
IO = 4.0 mA; VCC = 3.0 V 2.55 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A
IOZ OFF-state output current VI = VIH or VIL; VO = 0 V to 3.6V;
VCC = 0 V to 3.6 V 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6V;
VCC=0Vto 0.2 V 0.6 A
ICC supply current VI = GND or VCC; IO =0A;
VCC= 0.8 V to 3.6 V 0.9 A
ICC additional supply current VI = VCC 0.6 V; IO =0A;
VCC =3.3V
[1] -- 50 A
Tamb = 40 C to +125C
VIH HIGH-level input voltage VCC = 0.8 V 0.75 VCC -- V
VCC = 0.9 V to 1.95 V 0.70 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.25 VCCV
VCC = 0.9 V to 1.95 V - - 0.30 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
Table 7. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state[1] One input at VCC 0.6 V, other input at VCC or GND.
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.11- - V
IO = 1.1 mA; VCC = 1.1 V 0.6 VCC -- V
IO = 1.7 mA; VCC = 1.4 V 0.93 - - V
IO = 1.9 mA; VCC = 1.65 V 1.17 - - V
IO = 2.3 mA; VCC = 2.3 V 1.77 - - V
IO = 3.1 mA; VCC = 2.3 V 1.67 - - V
IO = 2.7 mA; VCC = 3.0 V 2.40 - - V
IO = 4.0 mA; VCC = 3.0 V 2.30 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33 VCCV
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A
IOZ OFF-state output current VI = VIH or VIL; VO = 0 V to 3.6V;
VCC = 0 V to 3.6 V 0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6V;
VCC=0Vto 0.2 V 0.75 A
ICC supply current VI = GND or VCC; IO =0A;
VCC= 0.8 V to 3.6 V 1.4 A
ICC additional supply current VI = VCC 0.6 V; IO =0A;
VCC =3.3V
[1] -- 75 A
Table 7. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state
11. Dynamic characteristicsTable 8. Dynamic characteristicsVoltages are referenced to GND (ground=0 V); for test circuit see Figure11.
CL = 5 pFtpd propagation
delay
D to Q; see Figure7 [2]
VCC = 0.8 V - 21.4 - - - - - ns
VCC = 1.1 V to 1.3 V 2.8 6.6 13.5 2.6 13.8 2.6 15.2 ns
VCC = 1.4 V to 1.6 V 2.4 4.6 7.8 2.1 8.3 2.1 9.1 ns
VCC = 1.65 V to 1.95 V 1.9 3.7 6.2 1.6 6.7 1.6 7.3 ns
VCC = 2.3 V to 2.7 V 1.8 2.9 4.1 1.5 4.5 1.5 4.9 ns
VCC = 3.0 V to 3.6 V 1.5 2.5 3.5 1.2 4.0 1.2 4.5 ns
LE to Q; see Figure8 [2]
VCC = 0.8 V - 20.3 - - - - - ns
VCC = 1.1 V to 1.3 V 2.7 6.2 13.6 2.5 14.0 2.5 15.4 ns
VCC = 1.4 V to 1.6 V 2.3 4.4 7.6 2.0 8.5 2.0 9.3 ns
VCC = 1.65 V to 1.95 V 1.8 3.5 5.8 1.5 6.7 1.5 7.3 ns
VCC = 2.3 V to 2.7 V 1.5 2.6 4.0 1.3 4.4 1.3 4.8 ns
VCC = 3.0 V to 3.6 V 1.3 2.2 3.3 1.1 3.8 1.1 4.2 ns
ten enable time OEto Q; see Figure10 [3]
VCC = 0.8 V - 17.9 - - - - - ns
VCC = 1.1 V to 1.3 V 3.2 5.1 9.2 3.0 9.2 3.0 10.1 ns
VCC = 1.4 V to 1.6 V 2.6 3.8 5.8 2.4 6.1 2.4 6.7 ns
VCC = 1.65 V to 1.95 V 2.2 3.3 4.8 2.0 5.0 2.0 5.5 ns
VCC = 2.3 V to 2.7 V 2.0 2.7 3.8 1.8 4.0 1.8 4.4 ns
VCC = 3.0 V to 3.6 V 1.9 2.5 3.4 1.8 3.6 1.8 4.0 ns
tdis disable time OEto Q; see Figure10 [4]
VCC = 0.8 V - 9.4 - - - - - ns
VCC = 1.1 V to 1.3 V 2.9 4.2 7.5 2.8 7.9 2.8 8.7 ns
VCC = 1.4 V to 1.6 V 2.2 3.2 4.9 2.1 5.3 2.1 5.8 ns
VCC = 1.65 V to 1.95 V 2.2 3.0 4.4 2.1 4.9 2.1 5.4 ns
VCC = 2.3 V to 2.7 V 1.6 2.2 3.1 1.5 3.4 1.5 3.7 ns
VCC = 3.0 V to 3.6 V 1.9 2.6 3.3 1.8 3.6 1.8 4.0 ns
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state
CL = 10 pFtpd propagation
delay
D to Q; see Figure7 [2]
VCC = 0.8 V - 24.4 - - - - - ns
VCC = 1.1 V to 1.3 V 3.0 7.5 15.3 2.7 15.9 2.7 17.4 ns
VCC = 1.4 V to 1.6 V 2.6 5.3 9.0 2.2 9.4 2.2 10.3 ns
VCC = 1.65 V to 1.95 V 2.5 4.3 6.9 2.1 7.3 2.1 8.0 ns
VCC = 2.3 V to 2.7 V 2.0 3.5 4.8 1.8 5.3 1.8 5.9 ns
VCC = 3.0 V to 3.6 V 1.8 3.1 4.2 1.7 4.6 1.7 5.1 ns
LE to Q; see Figure8 [2]
VCC = 0.8 V - 23.3 - - - - - ns
VCC = 1.1 V to 1.3 V 2.9 7.1 15.4 2.7 16.1 2.7 17.7 ns
VCC = 1.4 V to 1.6 V 2.5 5.0 8.8 2.1 9.5 2.1 10.4 ns
VCC = 1.65 V to 1.95 V 2.3 4.1 6.6 2.0 7.3 2.0 8.1 ns
VCC = 2.3 V to 2.7 V 1.9 3.1 4.7 1.6 5.2 1.6 5.8 ns
VCC = 3.0 V to 3.6 V 1.7 2.8 4.0 1.4 4.4 1.4 4.9 ns
ten enable time OEto Q; see Figure10 [3]
VCC = 0.8 V - 21.2 - - - - - ns
VCC = 1.1 V to 1.3 V 3.7 6.0 10.6 3.4 10.6 3.4 11.7 ns
VCC = 1.4 V to 1.6 V 3.1 4.5 6.7 2.8 7.0 2.8 7.7 ns
VCC = 1.65 V to 1.95 V 2.7 3.9 5.5 2.5 5.8 2.5 6.4 ns
VCC = 2.3 V to 2.7 V 2.4 3.3 4.5 2.2 4.7 2.2 5.2 ns
VCC = 3.0 V to 3.6 V 2.3 3.1 4.1 2.2 4.3 2.2 4.7 ns
tdis disable time OEto Q; see Figure10 [4]
VCC = 0.8 V - 11.3 - - - - - ns
VCC = 1.1 V to 1.3 V 3.9 5.3 8.7 3.8 9.2 3.8 10.1 ns
VCC = 1.4 V to 1.6 V 3.0 4.1 5.8 2.9 6.2 2.9 6.8 ns
VCC = 1.65 V to 1.95 V 3.2 4.2 5.7 3.1 6.0 3.1 6.6 ns
VCC = 2.3 V to 2.7 V 2.3 3.0 4.0 2.2 4.3 2.2 4.7 ns
VCC = 3.0 V to 3.6 V 3.0 3.8 4.7 2.9 5.0 2.9 5.5 ns
Table 8. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V); for test circuit see Figure11.
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state
CL = 15 pFtpd propagation
delay
D to Q; see Figure7 [2]
VCC = 0.8 V - 27.3 - - - - - ns
VCC = 1.1 V to 1.3 V 3.5 8.3 16.9 3.2 17.5 3.2 19.2 ns
VCC = 1.4 V to 1.6 V 3.1 5.9 9.6 2.7 10.5 2.7 11.6 ns
VCC = 1.65 V to 1.95 V 2.6 4.8 7.6 2.2 8.5 2.2 9.3 ns
VCC = 2.3 V to 2.7 V 2.5 3.9 5.5 2.2 5.9 2.2 6.5 ns
VCC = 3.0 V to 3.6 V 2.2 3.6 4.9 1.8 5.5 1.8 6.0 ns
LE to Q; see Figure8 [2]
VCC = 0.8 V - 26.1 - - - - - ns
VCC = 1.1 V to 1.3 V 3.3 7.9 17.3 3.0 18.0 3.0 19.8 ns
VCC = 1.4 V to 1.6 V 3.0 5.6 9.7 2.5 10.7 2.5 11.8 ns
VCC = 1.65 V to 1.95 V 2.5 4.6 7.4 2.2 8.3 2.2 9.1 ns
VCC = 2.3 V to 2.7 V 2.3 3.6 5.3 2.0 5.9 2.0 6.4 ns
VCC = 3.0 V to 3.6 V 2.1 3.2 4.6 1.8 5.1 1.8 5.6 ns
ten enable time OEto Q; see Figure10 [3]
VCC = 0.8 V - 24.6 - - - - - ns
VCC = 1.1 V to 1.3 V 4.1 6.8 12.1 3.8 12.1 3.8 13.3 ns
VCC = 1.4 V to 1.6 V 3.5 5.1 7.5 3.2 7.9 3.2 8.7 ns
VCC = 1.65 V to 1.95 V 3.1 4.4 6.1 2.8 6.5 2.8 7.2 ns
VCC = 2.3 V to 2.7 V 2.8 3.7 5.0 2.5 5.3 2.5 5.8 ns
VCC = 3.0 V to 3.6 V 2.6 3.5 4.7 2.5 4.9 2.5 5.4 ns
tdis disable time OEto Q; see Figure10 [4]
VCC = 0.8 V - 13.1 - - - - - ns
VCC = 1.1 V to 1.3 V 4.9 6.5 9.8 4.8 10.4 4.8 11.4 ns
VCC = 1.4 V to 1.6 V 3.9 5.0 6.8 3.8 7.3 3.8 8.0 ns
VCC = 1.65 V to 1.95 V 4.2 5.3 6.9 4.1 7.3 4.1 8.0 ns
VCC = 2.3 V to 2.7 V 3.0 3.8 4.8 2.9 5.1 2.9 5.6 ns
VCC = 3.0 V to 3.6 V 4.1 5.0 6.1 4.0 6.4 4.0 7.0 ns
Table 8. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V); for test circuit see Figure11.
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state
CL = 30 pFtpd propagation
delay
D to Q; see Figure7 [2]
VCC = 0.8 V - 35.9 - - - - - ns
VCC = 1.1 V to 1.3 V 4.0 10.6 22.1 3.7 23.3 3.7 25.6 ns
VCC = 1.4 V to 1.6 V 3.6 7.5 12.3 3.5 13.6 3.5 15.0 ns
VCC = 1.65 V to 1.95 V 3.5 6.2 9.5 3.2 10.5 3.2 11.5 ns
VCC = 2.3 V to 2.7 V 3.3 5.1 6.9 2.9 7.6 2.9 8.3 ns
VCC = 3.0 V to 3.6 V 3.0 4.7 6.4 2.9 7.2 2.9 7.9 ns
LE to Q; see Figure8 [2]
VCC = 0.8 V - 34.8 - - - - - ns
VCC = 1.1 V to 1.3 V 3.9 10.2 22.2 3.7 23.5 3.7 25.9 ns
VCC = 1.4 V to 1.6 V 3.5 7.2 12.4 3.4 13.7 3.4 15.1 ns
VCC = 1.65 V to 1.95 V 3.3 5.9 9.5 3.0 10.5 3.0 11.6 ns
VCC = 2.3 V to 2.7 V 3.1 4.8 6.8 2.7 7.5 2.7 8.2 ns
VCC = 3.0 V to 3.6 V 2.9 4.4 6.1 2.6 7.0 2.6 7.7 ns
ten enable time OEto Q; see Figure10 [3]
VCC = 0.8 V - 34.5 - - - - - ns
VCC = 1.1 V to 1.3 V 5.5 9.1 16.2 4.9 16.2 4.9 17.8 ns
VCC = 1.4 V to 1.6 V 4.6 6.7 9.9 4.2 10.5 4.2 11.6 ns
VCC = 1.65 V to 1.95 V 4.2 5.7 7.9 3.7 8.6 3.7 9.5 ns
VCC = 2.3 V to 2.7 V 3.6 4.9 6.4 3.4 6.9 3.4 7.6 ns
VCC = 3.0 V to 3.6 V 3.4 4.7 6.1 3.3 6.5 3.3 7.2 ns
tdis disable time OEto Q; see Figure10 [4]
VCC = 0.8 V - 19.2 - - - - - ns
VCC = 1.1 V to 1.3 V 8.0 9.9 13.7 7.9 14.5 7.9 16.0 ns
VCC = 1.4 V to 1.6 V 6.3 7.7 9.7 6.2 10.5 6.2 11.6 ns
VCC = 1.65 V to 1.95 V 7.3 8.7 10.6 7.2 11.3 7.2 12.4 ns
VCC = 2.3 V to 2.7 V 5.2 6.2 7.5 5.1 7.8 5.1 8.6 ns
VCC = 3.0 V to 3.6 V 7.5 8.8 10.2 7.4 10.5 7.4 11.6 ns
CL = 5 pF, 10 pF, 15 pF and 30 pF pulse width LE HIGH; see Figure8
VCC = 0.8 V - 4.0 - - - - - ns
VCC = 1.1 V to 1.3 V - 0.7 - 2.1 - 2.1 - ns
VCC = 1.4 V to 1.6 V - 0.5 - 1.3 - 1.3 - ns
VCC = 1.65 V to 1.95 V - 0.4 - 1.0 - 1.0 - ns
VCC = 2.3 V to 2.7 V - 0.3 - 0.8 - 0.8 - ns
VCC = 3.0 V to 3.6 V - 0.2 - 0.8 - 0.8 - ns
Table 8. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V); for test circuit see Figure11.
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-statetsu(H) set-up time
HIGH
DtoLE; see Figure9
VCC = 0.8 V - 4.6 - - - - - ns
VCC = 1.1 V to 1.3 V - 0.9 - 2.2 - 2.2 - ns
VCC = 1.4 V to 1.6 V - 0.6 - 1.4 - 1.4 - ns
VCC = 1.65 V to 1.95 V - 0.4 - 1.0 - 1.0 - ns
VCC = 2.3 V to 2.7 V - 0 - 0.6 - 0.6 - ns
VCC = 3.0 V to 3.6 V - 0.1 - 0.4 - 0.4 - ns
tsu(L) set-up time
LOW
DtoLE; see Figure9
VCC = 0.8 V - 4.0 - - - - - ns
VCC = 1.1 V to 1.3 V - 1.2 - 2.7 - 2.7 - ns
VCC = 1.4 V to 1.6 V - 0.7 - 1.5 - 1.5 - ns
VCC = 1.65 V to 1.95 V - 0.6 - 1.2 - 1.2 - ns
VCC = 2.3 V to 2.7 V - 0.4 - 0.9 - 0.9 - ns
VCC = 3.0 V to 3.6 V - 0.3 - 0.7 - 0.7 - ns hold time D to LE HIGH or LOW;
see Figure9
VCC = 0.8 V - 4.6 - - - - - ns
VCC = 1.1 V to 1.3 V - 0.9 - 0.1 - 0.1 - ns
VCC = 1.4 V to 1.6 V - 0.6 - 0.1 - 0.1 - ns
VCC = 1.65 V to 1.95 V - 0.4 - 0 - 0 - ns
VCC = 2.3 V to 2.7 V - 0.2 - 0.2 - 0.2 - ns
VCC = 3.0 V to 3.6 V - 0.1 - 0.3 - 0.3 - ns
Table 8. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V); for test circuit see Figure11.
NXP Semiconductors 74AUP1G373
Low-power D-type transparent latch; 3-state[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPHZ and tPLZ.
[5] All specified values are the average typical values over all stated loads.
[6] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;
(CL VCC2fo)= sum of the outputs; = number of inputs switching.
12. WaveformsCPD power
dissipation
capacitance
fi = 1 MHz; VI= GND to VCC [5][6]
output enabled
VCC = 0.8 V - 2.0 - - - - - pF
VCC = 1.1 V to 1.3 V - 2.0 - - - - - pF
VCC = 1.4 V to 1.6 V - 2.0 - - - - - pF
VCC = 1.65 V to 1.95 V - 2.1 - - - - - pF
VCC = 2.3 V to 2.7 V - 2.4 - - - - - pF
VCC = 3.0 V to 3.6 V - 2.8 - - - - - pF
Table 8. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V); for test circuit see Figure11.
