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74ALVCF322835FAIN/a49avaiLow Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26-Ohm Series Resistors in Outputs


74ALVCF322835 ,Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26-Ohm Series Resistors in OutputsFeaturesThe 74ALVCF322835 low voltage 36-bit universal bus

74ALVCF322835
Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26-Ohm Series Resistors in Outputs
74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in Outputs May 2002 Revised May 2002 74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in Outputs General Description Features The 74ALVCF322835 low voltage 36-bit universal busCompatible with PC133 DIMM module specifications driver combines D-type latches and D-type flip-flops to1.65V to 3.6V V specifications provided CC allow data flow in transparent, latched and clocked modes. 3.6V tolerant outputs Data flow is controlled by output-enable (OE), latch-enable 26Ω series resistors in outputs (LE), and clock (CLK) inputs. The device operates in t (CLK to O ) Transparent Mode when LE is held HIGH. The device PD n operates in clocked mode when LE is LOW and CLK is tog- 3.7 ns max for 3.0V to 3.6V V CC gled. Data transfers from the Inputs (I ) to Outputs (O ) on n n 4.6 ns max for 2.3V to 2.7V V CC a Positive Edge Transition of the Clock. When OE is LOW, 7.4 ns max for 1.65V to 1.95V V CC the output data is enabled. When OE is HIGH the output Power-down high impedance outputs port is in a high impedance state. Latchup conforms to JEDEC JED78 The 74ALVCF322835 is designed with 26Ω series resistors ESD performance: in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus Human body model > 2000V transceivers/transmitters. Machine model >200V The 74ALVCF322835 is designed for low voltage (1.65V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74ALVCF322835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Ordering Code: Package Order Number Package Description Number 74ALVCF322835G BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1) (Note 2) Note 1: Ordering Code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 DS500741
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