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74ALVC16841MTDXFAIN/a122avaiLow Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs


74ALVC16841MTDX ,Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and OutputsFunctional DescriptionThe 74ALVC16841 contains twenty D-type latches with D-type input changes. Whe ..
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74ALVC16841MTDX
Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74ALVC16841 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs November 2001 Revised November 2001 74ALVC16841 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC16841 contains twenty non-inverting latches with � 1.65V–3.6V V supply operation CC 3-STATE outputs and is intended for bus oriented applica- � 3.6V tolerant inputs and outputs tions. The device is byte controlled. The flip-flops appear � t (D to O ) PD n n transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time 3.5 ns max for 3.0V to 3.6V V CC is latched. Data appears on the bus when the Output 3.9 ns max for 2.3V to 2.7V V CC Enable (OE) is LOW. When OE is HIGH, the outputs are in 6.8 ns max for 1.65V to 1.95V V a high impedance state. CC � Power-off high impedance inputs and outputs The 74ALVC16841 is designed for low voltage (1.65V to 3.6V) V applications with I/O compatibility up to 3.6V. CC � Supports live insertion and withdrawal (Note 1) The 74ALVC16841 is fabricated with an advanced CMOS � Uses patented noise/EMI reduction circuitry technology to achieve high speed operation while maintain- � Latchup conforms to JEDEC JED78 ing low CMOS power dissipation. � ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n LE Latch Enable Input n D –D Inputs 0 19 O –O Outputs 0 19 © 2001 DS500690
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