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74AHC573-74AHC573PW-74AHCT573-74AHCT573PW
Octal D-type transparent latch; 3-state
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
FEATURES ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000V EIA/JESD22-A115-A
exceeds 200V
CDM EIA/JESD22-C101
exceeds 1000V Balanced propagation delays All inputs have Schmitt-trigger
actions Common 3-state output enable
input Functionally identical to the ‘563’
and ‘373’ Inputs acceptsvoltageshigher than
VCC For AHC only:
operates with CMOS input levels For AHCT only:
operates with TTL input levels Specified from
−40to +85 and +125 °C.
DESCRIPTIONThe 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT573 are octal D-type transparent latches featuring separate
D-type inputs for each latch and 3-state outputs for bus oriented applications. Latch Enable (LE) input andan Output Enable (OE) input are commontoall
latches.
The ‘573’ consistsof eight D-type transparent latches with 3-state true outputs.
WhenLEis HIGH, dataat theDn inputs enters the latches.In this condition the
latches are transparent, i.e. a latch output will change state each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present at the
D-inputsa set-up time preceding the HIGH-to-LOW transitionof LE. When OE LOW, the contentsof the8 latches are availableat the outputs. When OEis
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The ‘573’is functionally identicalto the ‘533’, ‘563’ and ‘373’, but the ‘533’ and
‘563’ have inverted outputs and the ‘563’ and ‘373’ have a different pin
arrangement.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf≤ 3.0 ns.
Notes CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi+∑ (CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz; (CL× VCC2×fo)= sum of outputs;= output load capacitance in pF;
VCC= supply voltage in Volts. The condition is VI= GNDto VCC.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
FUNCTION TABLESee note1.
Note H= HIGH voltage level;= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;= LOW voltage level;= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;= high-impedance OFF-state.
ORDERING INFORMATION
PINNING
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).
Notes The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
DC CHARACTERISTICS
74AHC familyOver recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
74AHCT familyOver recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
AC CHARACTERISTICS
74AHC573GND=0 V; tr =tf≤ 3.0 ns.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
Notes Typical values at VCC= 3.3V. Typical values at VCC= 5.0V.
