74AHC574D-74AHCT574PW Fast Delivery |IC PHOENIX CO.,LIMITED

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74AHC574D-74AHCT574PW
Octal D-type flip-flop; positive edge-trigger; 3-state
General descriptionThe 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with Low Power Schottky TTL (LSTTL). They are speciﬁedin compliance with
JEDEC standard no. 7A.
The 74AHC574; 74AHCT574 are octal D-type ﬂip-ﬂops featuring separate D-type inputs
for each ﬂip-ﬂop and 3-state outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all ﬂip-ﬂops.
The8 ﬂip-ﬂops will store the stateof their individual D-inputs that meet the set-up and hold
times requirements on the LOW-to-HIGH CP transition.
When OEis LOW the contentsof the8 ﬂip-ﬂops are availableat the outputs. When OEis
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the ﬂip-ﬂops.
The 74AHC574; 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but
has non-inverting outputs. The 74AHC574; 74AHCT574 is functionally identical to
the 74AHC374; 74AHCT374, but has a different pinning. Features Balanced propagation delays All inputs have a Schmitt-trigger action 3-state non-inverting outputs for bus orientated applications 8-bit positive, edge-triggered register Independent register and 3-state buffer operation Common 3-state output enable input For 74AHC574 only: operates with CMOS input levels For 74AHCT574 only: operates with TTL input levels ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C
74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
Rev. 02 — 24 January 2008 Product data sheet
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Ordering information Functional diagram
Table 1. Ordering information
74AHC574D −40°Cto +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHCT574D
74AHC574PW −40°Cto +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74AHCT574PW
74AHC574BQ −40°Cto +125°C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quadﬂat package;no leads;20 terminals;
body 2.5× 4.5× 0.85 mm
SOT764-1
74AHCT574BQ
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 3-state output enable input (active LOW)
D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0V) 11 clock input (LOW-to-HIGH, edge triggered)
Q[0:7] 19,18, 17, 16, 15, 14,13,12 3-state ﬂip-ﬂop output
VCC 20 supply voltage
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Functional description
[1]H= HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;= LOW voltage level;= LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;= high-impedance OFF-state;= LOW-to-HIGH clock transition. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70°C.
[3] Ptot derates linearly with 5.5 mW/K above 60°C.
[4] Ptot derates linearly with 4.5 mW/K above 60°C.
Table 3. Function table[1]
Load and read register L ↑ lL L ↑ hH H
Load register and disable output H ↑ lL Z ↑ hH Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO< −0.5 V orVO >VCC+ 0.5V [1]- ±20 mA output current VO = −0.5 V to (VCC+ 0.5V) - ±25 mA
ICC supply current - 75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C
SO20 package [2]- 500 mW
TSSOP20 package [3]- 500 mW
DHVQFN20 package [4]- 500 mW
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Recommended operating conditions Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 - 5.5 0 - 5.5 V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔV input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V
VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
For type 74AHC574
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V
IOZ OFF-state
output current
VI =VIH or VIL; =VCCor GND;
VCC= 5.5V ±0.25 - ±2.5 - ±10.0 μA input leakage
current= 5.5 Vor GND;
VCC=0V to 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state input
capacitance 3.0 10 - 10 - 10 pF output
capacitance 4.0 - - - - - pF
For type 74AHCT574
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 50μA - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V
IOZ OFF-state
output current
per input pin; VI =VIH or VIL;
VCC= 5.5 V; IO= 0 A; =VCCor GND;
other pinsat VCC or GND ±0.25 - ±2.5 - ±10.0 μA input leakage
current= 5.5 Vor GND;
VCC=0V to 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 4.0 - 40 - 80 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; IO= 0 A;
other pinsat VCC or GND;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance 3 10 - 10 - 10 pF output
capacitance 4.0 - - - - - pF
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V. For test circuit see Figure 10.
For type 74AHC574
tpd propagation
delayto Qn; see Figure7 [2]
VCC = 3.0 V to 3.6 V=15pF - 6.5 13.2 1.0 15.5 1.0 16.5 ns=50pF - 9.3 16.7 1.0 19.0 1.0 21.0 ns
VCC = 4.5 V to 5.5 V=15pF - 4.4 8.6 1.0 10.0 1.0 11.0 ns=50pF 6.2 10.6 1.0 12.0 1.0 13.5 ns
ten enable time OEto Qn; see Figure9 [1]
VCC = 3.0 V to 3.6 V=15pF - 5.7 12.8 1.0 15.0 1.0 16.0 ns=50pF - 8.2 16.3 1.0 18.5 1.0 20.5 ns
VCC = 4.5 V to 5.5 V=15pF - 4.2 9.0 1.0 10.5 1.0 11.5 ns=50pF - 5.9 11.0 1.0 12.5 1.0 14.0 ns
tdis disable time OEto Qn; see Figure9 [2]
VCC = 3.0 V to 3.6 V=15pF - 6.3 13.0 1.0 15.0 1.0 16.5 ns=50pF - 9.1 15.0 1.0 17.0 1.0 19.0 ns
VCC = 4.5 V to 5.5 V=15pF - 4.3 9.0 1.0 10.5 1.0 11.5 ns=50pF - 6.9 10.1 1.0 11.5 1.0 13.0 ns
fmax maximum
frequency
CP; see Figure7
VCC = 3.0 V to 3.6 V=15pF 80 125 - 65 - 65 - MHz=50pF 50 75 - 45 - 45 - MHz
VCC = 4.5 V to 5.5 V=15pF 130 180 - 110 - 110 - MHz=50pF 85 115 - 75 - 75 - MHz pulse width CP; HIGH or LOW;
see Figure7
VCC= 3.0 V to 3.6 V; =50pF
5.0 - - 5.0 - 5.0 - ns
VCC= 4.5 V to 5.5 V; =50pF
5.0 - - 5.0 - 5.0 - ns
NXP Semiconductors 74AHC574; 74AHCT574
Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state
tsu set-up time Dnto CP; see Figure8
VCC= 3.0 V to 3.6 V; =50pF
3.5 - - 3.5 - 3.5 - ns
VCC= 4.5 V to 5.5 V; =50pF
3.0 - - 3.0 - 3.0 - ns hold time Dn to CP; see Figure8
VCC= 3.0 V to 3.6 V; =50pF
1.5 - - 1.5 - 1.5 - ns
VCC= 4.5 V to 5.5 V; =50pF
1.5 - - 1.5 - 1.5 - ns
CPD power
dissipation
capacitance=50 pF; fi = 1 MHz;= GNDto VCC
[3] -10 - - - - - pF
For type 74AHCT574
tpd propagation
delayto Qn; see Figure7 [2]
VCC = 4.5 V to 5.5 V=15pF - 4.4 8.6 1.0 10.0 1.0 11.0 ns=50pF - 6.3 10.6 1.0 12.0 1.0 13.5 ns
ten enable time OEto Qn; see Figure9
VCC = 4.5 V to 5.5 V=15pF - 4.3 9.0 1.0 10.5 1.0 11.5 ns=50pF - 6.1 11.0 1.0 12.5 1.0 14.0 ns
tdis disable time OEto Qn; see Figure9 [2]
VCC = 4.5 V to 5.5 V=15pF - 4.3 9.0 1.0 10.5 1.0 11.5 ns=50pF - 6.2 10.1 1.0 11.5 1.0 13.0 ns
fmax maximum
frequency
CP; see Figure7
VCC = 4.5 V to 5.5 V=15pF 130 180 - 110 - 110 - MHz=50pF 85 115 - 75 - 75 - MHz pulse width CP; HIGH or LOW;
see Figure7
VCC= 4.5 V to 5.5V; =50pF
5.0 - - 5.5 - 5.5 - ns
tsu set-up time Dnto CP; see Figure8
VCC= 4.5 V to 5.5V; =50pF
3.0 - - 3.5 - 3.5 - ns
Table 7. Dynamic characteristics …continued
GND = 0 V. For test circuit see Figure 10.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC574D	SOP72	N/a	1802	avai	Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574D	NXP	N/a	1000	avai	Octal D-type flip-flop; positive edge-trigger; 3-state
74AHCT574PW	NXP	N/a	22500	avai	Octal D-type flip-flop; positive edge-trigger; 3-state