74AHC573PW-74AHCT573PW Fast Delivery |IC PHOENIX CO.,LIMITED

74AHC573PW ,Octal D-type transparent latch; 3-stateapplications. A latch enable input (LE) and an output enable input (OE) are common to all latches.W ..
74AHC573PW ,Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEET74AHC573; 74AHCT573Octal D-type transparent latch;3-stateProduct speci ..
74AHC573PW ,Octal D-type transparent latch; 3-stateGeneral descriptionThe 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatibl ..
74AHC573PW ,Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEET74AHC573; 74AHCT573Octal D-type transparent latch;3-stateProduct speci ..
74AHC574 ,Octal D-type flip-flop; positive edge-trigger; 3-stateapplications compatible with low power Schottky TTL (LSTTL). They are specified incompliance with J ..
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74HC373N ,Octal D-type transparent latch; 3-stateGeneral descriptionThe 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible ..
74HC373PW ,74HC/HCT373; Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC374 ,3-stateMAXIMUM RATINGSÎÎ Symbol Parameter Value UnitThis device contains protectioncircuitry to guard agai ..
74HC374D ,74HC/HCT374; Octal D-type flip-flop; positive edge-trigger; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC374DB ,Octal D-type flip-flop; positive edge-trigger; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC374N ,74HC/HCT374; Octal D-type flip-flop; positive edge-trigger; 3-stateGENERAL DESCRIPTIONThe “374” is functionally identical to the “534”, but hasThe 74HC/HCT374 are hig ..

74AHC573PW-74AHCT573PW
Octal D-type transparant latch; 3-state
1. General description
The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring
separate D-type inputs for each latch and 3-state true outputs for bus oriented
applications. A latch enable input (LE) and an output enable input (OE) are common to all
latches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
Dn input changes. When pin LE is LOW, the latches store the information that is present
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, but
has a different pin arrangement.
2. Features and benefits Balanced propagation delays All inputs have a Schmitt trigger action Common 3-state output enable input Functionally identical to the 74AHC373; 74AHCT373 Inputs accept voltages higher than VCC Input levels: For 74AHC573: CMOS input level For 74AHCT573: TTL input level ESD protection: HBM EIA/JESD22-A114E exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101C exceeds 1000V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
Rev. 7 — 8 November 2011 Product data sheet
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74AHC573
74AHC573D 40Cto +125C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHC573PW 40Cto +125C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74AHC573BQ 40Cto +125C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74AHCT573
74AHCT573D 40Cto +125C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74AHCT573PW 40Cto +125C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74AHCT573BQ 40Cto +125C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 output enable input (active LOW)
D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0V) 11 latch enable (active HIGH)
Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output
VCC 20 supply voltage
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
6. Functional description
[1] H= HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;= LOW voltage level;= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;= high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table[1]
Enable and read register (transparent
mode) L L L H
Latch and read register L L l L L H
Latch register and disable outputs H L l L Z Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5V [1] 20 - mA
IOK output clamping current VO< 0.5 V orVO >VCC +0.5V [1] 20 +20 mA output current VO = 0.5 V to (VCC +0.5V) 25 +25 mA
ICC supply current - +75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C [2]- 500 mW
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Operating conditions
74AHC573
VCC supply voltage 2.0 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V
VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHCT573
VCC supply voltage 4.5 5.0 5.5 V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
74AHC573
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL = 50 A; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - - V = 50 A; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - - V = 50 A; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - - V = 4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - - V = 8.0 mA; VCC= 4.5 V 3.94 - - 3.80 - 3.70 - - V
VOL LOW-level
output voltage = VIH or VIL = 50 A; VCC= 2.0 V - 0 0.1 - 0.1 - - 0.1 V = 50 A; VCC= 3.0 V - 0 0.1 - 0.1 - - 0.1 V = 50 A; VCC= 4.5 V - 0 0.1 - 0.1 - - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - - 0.55 V
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
IOZ OFF-state
output current
VI =VIH or VIL; =VCCor GND;
VCC =5.5V 0.25 - 2.5 - - 10.0 A input leakage
current =VCCor GND;
VCC =0Vto 5.5V - 0.1 - 1.0 - - 2.0 A
ICC supply currentVI =VCCor GND;IO =0A;
VCC =5.5V - 4.0 - 40 - - 80 A input
capacitance =VCCor GND - 3 10 - 10 - - 10 pF output
capacitance - - - - - 10 pF
74AHCT573
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V = 50A 4.4 4.5 - 4.4 - 4.4 - - V = 8.0 mA 3.94 - - 3.80 - 3.70 - - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 50 A- 0 0.1 - 0.1 - - 0.1 V = 8.0 mA - - 0.36 - 0.44 - - 0.55 V
IOZ OFF-state
output current
VI =VIH or VIL; =VCCor GND per input
pin; other inputs at VCC or
GND; IO =0 A 0.25 - 2.5 - - 10.0 A input leakage
current= 5.5 Vor GND;
VCC =0Vto 5.5V - 0.1 - 1.0 - - 2.0 A
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC =5.5V - 4.0 - 40 - - 80 A
ICC additional
supply current
per input pin; =VCC 2.1 V; IO =0 A;
other pinsat VCC or GND;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - - 1.5 mA input
capacitance =VCCor GND - 3 10 - 10 - - 10 pF output
capacitance - - - - - 10 pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0V).
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
10. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure11.
74AHC573
tpd propagation
delayto Qn; see Figure7 [2]
VCC = 3.0 V to 3.6 V=15pF - 5.5 11.0 1.0 13.0 1.0 14.0 ns=50pF - 7.8 14.5 1.0 16.5 1.0 18.5 ns
VCC = 4.5 V to 5.5 V=15pF - 3.9 6.8 1.0 8.0 1.0 8.5 ns=50pF - 5.5 8.8 1.0 10.0 1.0 11.0 nsto Qn; see Figure8 [2]
VCC = 3.0 V to 3.6 V=15pF - 5.8 11.9 1.0 14.0 1.0 15.0 ns=50pF - 8.3 15.4 1.0 17.5 1.0 19.5 ns
VCC = 4.5 V to 5.5 V=15pF - 4.2 7.7 1.0 9.0 1.0 10.0 ns=50pF - 5.9 9.7 1.0 11.0 1.0 12.5 ns
ten enable time OEto Qn; see Figure9 [3]
VCC = 3.0 V to 3.6 V=15pF - 5.8 11.5 1.0 13.5 1.0 14.5 ns=50pF - 8.3 15.0 1.0 17.0 1.0 19.0 ns
VCC = 4.5 V to 5.5 V=15pF - 4.4 7.7 1.0 9.0 1.0 10.0 ns=50pF - 6.3 9.7 1.0 11.0 1.0 12.5 ns
tdis disable time OEto Qn; see Figure9 [4]
VCC = 3.0 V to 3.6 V=15pF - 6.8 11.0 1.0 13.0 1.0 14.0 ns=50pF - 9.7 14.5 1.0 16.5 1.0 18.5 ns
VCC = 4.5 V to 5.5 V=15pF - 4.6 7.7 1.0 9.0 1.0 10.0 ns=50pF - 7.4 9.7 1.0 11.0 1.0 12.5 ns pulse width LE HIGH; see Figure8
VCC= 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
VCC= 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time Dnto LE; see Figure10
VCC= 3.0 V to 3.6 V 3.5 - - 3.5 - 3.5 - ns
VCC= 4.5 V to 5.5 V 3.5 - - 3.5 - 3.5 - ns
NXP Semiconductors 74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0V).
[2] tpd is the same as tPHL and tPLH.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs. hold time Dn to LE; see Figure10
VCC= 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns
VCC= 4.5 V to 5.5 V 1.5 - - 1.5 - 1.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; =GNDto VCC
[5] -12 - - - - - pF
74AHCT573; VCC = 4.5 V to 5.5 V
tpd propagation
delayto Qn; see Figure7 [2]=15pF - 3.5 5.5 1 6.5 1 7.0 ns=50pF - 4.9 7.5 1 8.5 1 9.5 nsto Qn; see Figure8 [2]=15pF - 3.9 6.0 1 7.0 1 7.5 ns=50pF - 5.5 8.5 1 9.5 1 11.0 ns
ten enable time OEto Qn; see Figure9 [3]=15pF - 4.1 6.5 1 7.5 1 8.5 ns=50pF - 5.9 8.5 1 10.0 1 11.0 ns
tdis disable time OEto Qn; see Figure9 [4]=15pF - 4.5 6.5 1 7.5 1 8.5 ns=50pF - 6.4 9.0 1 10.0 1 11.5 ns pulse width LE HIGH; see Figure8 5.0 - - 5.0 - 5.0 - ns
tsu set-up time Dnto LE; see Figure10 3.5 - - 3.5 - 3.5 - ns hold time Dn to LE; see Figure10 1.5 - - 1.5 - 1.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; =GNDto VCC
[5] -18 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure11.

Partno	Mfg	Dc	Qty	Available	Descript
74AHC573PW		N/a	91	avai	Octal D-type transparent latch; 3-state
74AHC573PW	Pb-free	N/a	2000	avai	Octal D-type transparent latch; 3-state
74AHCT573PW	TI	N/a	158	avai	Octal D-type transparant latch; 3-state